i am project trainee in E-infochip,Ahmedabad,Gujarat.
Now, I am doing my final year project " netlist to GDS-II on networking block closure with optimizing timing.
I'm a VLSI fresher pursuing M.E. in VLSI system design from Marwadi education foundation group of institute , Rajkot and looking for a fresh start as a designer anywhere in India and also abroad. I've been designing circuits in EDA tools mainly Cadence, Mentor-graphics and ADS & have a gamut of experience in designing analog & digital circuits during my post graduation.
I am interested in (physical design) Back-End IC Design.
i am working on Synopsys tools.
B.E from Shantilal shah Engineering college (Bhavnagar).