ºÝºÝߣ

Bengaluru Area, India India

Senior Engineer at Qualcomm

Electronics / Computer Hardware

• Working on Processor Optimization Packages (http://www.arm.com/products/physical-ip/processor-optimization-pack/index.php)' • Worked on multiple ARM core implementation in 28nm technologies across Cortex-A7 and Cortex-A35 configurations. • Experience include Block-level Physical Design from netlist till GDS (including synthesis, Floorplaning , Placement, Clock tree synthesis ,Routing and STA, Timing closure . • Hands-on experience with Synopsys ASIC design Flows (DC,ICC,PT) • Pushing ARM cores & Physical IPs for best PPA numbers. • Timing and Leakage ECO. • Signal EM analysis. • Test Chip timing correlation among Silicon data, STA results & simulated results. • Architecture determina...