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Graduate student in Electrical Engineering actively Seeking Full Time in the field of digital VLSI/ASIC design from Jan 2016.


Highlights:

• Proficient in Semi-Custom and Full Custom VLSI Design, Memory design and  ASIC Design flow-Placement and routing, Static Timing Analysis (STA) and RTL design and synthesis using Verilog and VHDL.

• Good hands on experience in Physical Design through Layout, placement and routing tools.

• Proficient in C, C++, Perl, VHDL and Verilog programming with good debugging skills.

Interests:

VLSI,New product design / development and verification, Technology Adoption, Electrical & Electronics design, 

Expertise:
•Hardware Description Languages : Ver

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