ASIC DFT Design Engineer with 1 year of experience.
Experience on Synopsys, Cadence tool chains.
Experience on 28nm, 180nm for DFT Scan Insertion , ATPG Pattern Generation for Stuck-at & Transition Fault Models,Test Coverage Improvement for SoC and IP.
Specialties:
HDL : Verilog
Synopsys Tools : DFT Compiler, TetraMAX
Cadence Tool : Encounter Test , RTL Compiler NC Verilog
Scripting : Perl
I like to excel in my field through hard work, skills, research and perseverance by taking up challenging assignments, responsibilities; with an aim of growth and career advancement. I am an ambitious person and like to strive for development in order to achieve personal as well as organizational g...