profilePage

Currently working as Teaching Assistant at San Jose State University

Graduate student majoring in Electrical Engineering (Specialization- Digital Design) at San Jose State University (SJSU) actively looking for part time/full time opportunities.

Interests: Digital Design, ASIC, Verification, Digital design of DSP and Communications

Technical Skills

- Key skills: RTL Design, Synthesis and Verification, Timing analysis and solving problems.

- Tools: Behavioral Simulation - Synopsys VCS, Synopsys Design Vision, NCVerilog, Icarus Verilog, ModelSim, ARM Keil μvision

Synthesis - Synopsys Design Compiler

FPGA tools- Altera Quartus II

Cadence

- Programming Languages: C, C++, Verilog, A...

�ݺ�ߣ