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Bengaluru Area, India India

Co-founder & Principal Engineer (ESD & Layout) at Krivi Semiconductor Private Limited

Electronics / Computer Hardware

Working on ESD, Reliability and Layout Designing of DDR Phy and its sub-components at Krivi, Bangalore. Previously worked on ESD, Reliability and Layout Design of DDRn-phy, Band Gap, PLL, DLL, specialty IO’s such as LVDS/sub-LVDS, USB, PCIX, Memory Card and General Purpose IO at ARM, Bangalore. Prior to this I started my career as a Trainee Engineer at Larsen & Toubro, Meter Engineering R&D, Mysore. Specialties: Expertise on mixed signal and Analog IO Layout designing, ESD Design and network simulations, Prenvention for Latchup, DFM (lfd/vcmp/cmp aware parasitic extraction), Coding, modifying, or reading DRC/LVS runsets, EM-IR analysis, Chip and I/O Modeling for System-level Power N.