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Ahmedabad Area, India India

ASIC Verification Engineer

Electronics / Computer Hardware

+Experience in RTL design & testing on FPGA development board. +Experience in Development of VIPs (Verification IPs) in System Verilog with methodology OVM/UVM. +Experience in Performing Code coverage & Functional coverage for protocol based test bench. +Experience in writing Assertions in SystemVerilog (SVA) for protocol timing analysis. +Worked extensively on the Cadence verification methodologies OVM. +Hands on experience with verification tools called Mentors'Questasim,Model-sim.