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Personal Information
Organization / Workplace
Bengaluru Area, India India
Occupation
Sr. Manager - Design Engg at AMD
Industry
Electronics / Computer Hardware
About
MBA, Southern Methodist University.SMU Dallas,Texas,99-01 M.S.E.E, University of South Florida. Tampa, Florida. 95-97 B.E. in electronics, REC(NIT). Bhopal University, India.89-93 IP , full chip SoC design, project/program mgmt, Design flow (R2G,functional+system verification, software infrastr.), lead global cross site SoC verification teams. Specialties: Seasoned semiconductor professional; 19 years of industry experience with startups and large US,European MNC's. Management experience includes building team from scratch, motivating and managing multiple teams/project mgr to excel and meet customer expectations; Managing customer interface/program mgmt of complex SoC’s,IP development..
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Presentations(12)Ìý

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Universal Chip interconnect Verification
Universal Chip interconnect VerificationUniversal Chip interconnect Verification
Universal Chip interconnect Verification
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An Approach to Overcome Modeling Inaccuracies for Performance Simulation Signoff of High-Speed SerDes
An Approach to Overcome Modeling  Inaccuracies for Performance Simulation Signoff  of High-Speed SerDesAn Approach to Overcome Modeling  Inaccuracies for Performance Simulation Signoff  of High-Speed SerDes
An Approach to Overcome Modeling Inaccuracies for Performance Simulation Signoff of High-Speed SerDes
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Unified methodology for effective correlation of soc power
Unified methodology for effective correlation of soc powerUnified methodology for effective correlation of soc power
Unified methodology for effective correlation of soc power
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Documents(1)Ìý

Thesis
ThesisThesis
Thesis
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