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I have 7 years of experience in IP designing and verification, architecture IP/micro level designing, algorithm analysis, Timing closure, Verification Test Plan creation. 

Currently Working in designing of Next Generation DRAM Memory Controller - DDR3,DDR2, Timing Closure, Architecture Review and Modification, STA, LINT, LEC, Verification Testplan, Checker, Assertions and setting various automation and analysis tool to increase productivity and debugging. 

• Expertise in complete EDA design flow, Micro Arch Design, RTL development, synthesis and optimization issues, and static timing analysis for high speed digital design.
• Expertise in RTL development in VHDL and VERILOG.
.• Expert

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