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Raleigh-Durham, North Carolina Area United States

Account Technical Executive at Cadence Design Systems

Technology / Software / Internet

Chip design engineer with knowledge of various aspects of the chip design process. Creative leader and team member. Responsible for design synthesis for a large network processor design. Currently providing both tool and methodology verification consulting expertise. Experience with SystemVerilog, Formal Verification, Open Verification Methodology (OVM), UVM, 'e', PSL, VHDL, and Verilog. Specialties: Functional Verification, Formal Verification, RTL Design, Static Timing Analysis, Verification Planning and Management, Synthesis, Object Oriented Programming, SystemVerilog, OVM, UVM