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Noida Area, India India

Member of Technical Staff at Calypto Design Systems

Technology / Software / Internet

Worked in Functional Verification and Formal Verification part of Chip Designing, with focus on compiler theory such as parsing, syntax tree and compiler optimizations. Worked on improving the quality of EDA tools through numerous bug fixes and enhancements; and in-depth testing in RTL languages such as Verilog and VHDL. Involved in many high quality, core simulator solutions for semi-conductor industry, with thorough insight of customer's expectations and our product's role.