Personal Information
Organization / Workplace
San Francisco Bay Area United States
Occupation
Senior Director Harware Engineer at eASIC
Industry
Electronics / Computer Hardware
About
Chartered Engineer, MIEE UK
Lead author of "Nano-CMOS Circuit and Physical Design" 2004 John Wiley with Forward by Professor Chenming Hu
Lead author of "Nano-CMOS DFM" Oct 2008 John Wiley
Saved >$24 million through a quick port of a high volume product to a second source foundry with no layout change, only selective implant changes at the mask level. Device shipped on first silicon without design tweaks(Nvidia)
Designed two 0.999u2 bitcells in 90nm, one each at Samsung and Chartered Semiconductor with native yield of about 80% on first silicon(Nvidia)
Improved ESD performance from sub 1KV to greater than 2KV and 450fF capacitance(Sun, Nvidia, Stretch)
Lead the development of the high...
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