Personal Information
Organization / Workplace
San Francisco Bay Area United States
Occupation
MS EE, VLSI | ASIC Design Engineer Intern, Team Lead | Versatile skill set | Leadership experience in SME for 4+ years
Industry
Electronics / Computer Hardware
About
Actively seeking a challenging role in design/verification of ASIC,FPGA,SoC.
MS Electrical Engineering from San Jose State University:
- Passionate about ASIC front-end development - Digital Design, Verification.
- 2.5 years of experience in logic design, verification using industry standard EDA/CAD tools used for debugging, simulation, synthesis, and other ASIC design flow steps.
- Proficient in Verilog, SystemVerilog, UVM, Python, OOP, C, C++, Unix shell scripting.
- Strong knowledge of computer architecture, ASIC, SoC design and verification.
- Team Lead, ASIC Design Engineer Intern at Scalable Systems Research Labs Inc. since Feb 2017 (5 months).
- Mentored a class of 100 as a Teach...
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