Working in the field of VLSI in Analog and Mixed Signal (AMS) domain for last 8 years
Work experience in Summary:
Layout of Analog blocks like Band-Gap References and Regulators
Design , Simulation and layout of standard general purpose I/O and DDR I/O Buffer cells
IBIS (IO Buffer Information Systems) Modelling.
Undergone training on Verilog-AMS
Graduate Degree in Electronics & Communication Engineering
PG Diploma in VLSI System Design(PGDVLSI) from CDAC, Pune, a Govt.of India Institute which had modules in Digital System Design, CMOS VLSI, HDL (Hardware Description Language), System Architecture, FPGA and CPLD devices
Certificate holder of Start Deutsche A1 lev