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Ryohei Kobayashi
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Assistant Professor
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OpenCL-ready High Speed FPGA Network for Reconfigurable High Performance Computing
OpenCL-ready High Speed FPGA Network for Reconfigurable High Performance Computing
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A survey of how to efficiently implement application-specific hardware on an FPGA
A survey of how to efficiently implement application-specific hardware on an FPGA
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A High-speed Verilog HDL Simulation Method using a Lightweight Translator
A High-speed Verilog HDL Simulation Method using a Lightweight Translator
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FACE: Fast and Customizable Sorting Accelerator for Heterogeneous Many-core Systems
FACE: Fast and Customizable Sorting Accelerator for Heterogeneous Many-core Systems
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