-VLSI Design Post Graduate student with 1 Year internship experience in VLSI design verification.
I have experience in various of domains and software.
-Bus protocols : AXI, AHB,SPI
-Memory controllers : UFS, RLDRAM, SDR-NAND flash
-VLSI design : Mixed signal design (Flash ADC Design using FinFET)
-Tool worked:HSpice,Cadence tool(RTL Compiler, virtuoso,Spectre), Mirowind
and Dsch tool, Questa Sim 10.0b.,Xillinx
-Software language :C, Verilog,System Verilog, UVM