Experience in Physical Design Implementation from Netlist to GDSII
Technology nodes: 10nm, 14nm, 28nm, 40nm
Strong understanding of entire Physical Design flow
Good knowledge of Floorplanning and PnR
Primetime STA tool and timing closure methodologies
Understanding of Physical Verification
Tools worked on:
Synopsys IC Compiler and ICC2
Cadence Encounter, Innovus
Synopsys Primetime, StarRC
Mentor Graphics Calibre (DRC, LVS)
Formality
Tweaker
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