/ http://www.slideshare.net/images/logo.gif / 際際滷Share feed for 際際滷shows by User: HerivaldoMaia https://cdn.slidesharecdn.com/profile-photo-HerivaldoMaia-48x48.jpg?cb=1608564997 I am EE, M.Sc. with 20+ years experience in designing and verifying SoC and FPGA devices including Xilinx, Altera. RTL Languages I use are VHDL and Verilog. I perform Lab debug using Logic Analyzers and Oscilloscopes.