/ http://www.slideshare.net/images/logo.gif / 際際滷Share feed for 際際滷shows by User: MohamedAbdellateef1 https://cdn.slidesharecdn.com/profile-photo-MohamedAbdellateef1-48x48.jpg?cb=1514492710 Front-End digital design and verification engineer with skills in these areas: Verilog/VHDL RTL coding Microprocessors/Microcontrollers SystemVerilog constrained random test environment Verification environment based on UVM methodology Assertion-Based Verification using SVA Verification tools (Synopsys VCS, Mentor Graphics QuestaSim) Familiarity with I/O & multimedia interfaces : PS2 Mouse/Keyboard UART I2C I2S S/PDIF HDMI