/ http://www.slideshare.net/images/logo.gif / 際際滷Share feed for 際際滷shows by User: NavneetUpadhyay2 https://cdn.slidesharecdn.com/profile-photo-NavneetUpadhyay2-48x48.jpg?cb=1422448575 Skilled in all phases of Front-end ASIC, FPGA design, including architecture development, writing specification, partitioning, RTL coding, function simulation, synthesis, timing analysis, and test insertion methodologies. Objective To achieve excellence in the field of Hardware Development, to be resourceful and optimistic and to pursue challenging career in VLSI design, then to establish myself as a pioneer in the field of Embedded systems and VLSI Technologies.