/ http://www.slideshare.net/images/logo.gif / ºÝºÝߣShare feed for ºÝºÝߣshows by User: SPatel4 https://cdn.slidesharecdn.com/profile-photo-SPatel4-48x48.jpg?cb=1422245528 • Full commitment to task and deliver high quality work according to schedule are my primary goals. • Area of Expertise: (1) ATPG pattern generation for stuck at model (2) ATPG pattern simulation for stuck at model for no-timing and timing simulation (3) ATPG pattern generation for TFT model (4) ATPG pattern simulation for TFT model for timing and no-timing simulations (5)scan insertion (6) DRC analysis (7)MBIST Logic understanding (8)JTAG boundary scan (9)EDT logic understanding Specialties: Languages: Verilog, C Protocolas : IEEE 1149.1 jtag boundary scan Scripting : PERL(begineer) Editors : gvim Tools : FastScan , DFTADVISOR,TetraMax , Questasim, Xilinx ISE , Mod...