/ http://www.slideshare.net/images/logo.gif / 際際滷Share feed for 際際滷shows by User: SatishKumarK https://cdn.slidesharecdn.com/profile-photo-SatishKumarK-48x48.jpg?cb=1655270819 SOC/ASIC/FPGA Design and Verification Engineer specialized in Front End cycle with 9 years of experience, majorly in client-facing roles. Team player with 6+ years of international exposure in China (Nokia Siemens Networks) and South Korea (Samsung Electronics, Uniquify Inc) Active participation on pre-silicon verification efforts, including FPGA Prototype, Design Verification (DV), hardware modeling frameworks Experience with Synthesis(DC), Gate Level Sim(NC-sim, VCS), Formality (Synopsis) and debugging tools verdi , Linting with Ascent, Ascent IIV, CDC tools meridian and Spy-Glass. Multiple Project Experience with FPGA tools Xilinx (ISE/Vivado) and Quartus Developing and debugging e...