/ http://www.slideshare.net/images/logo.gif / ºÝºÝߣShare feed for ºÝºÝߣshows by User: ThulasiReddy4 https://cdn.slidesharecdn.com/profile-photo-ThulasiReddy4-48x48.jpg?cb=1523607940 Perseverance towards chip design and verification . Dedication, Determination, & DISCIPLINE are my strength's. B.Tech ---> JNTU (ECE - 74%) M.Tech ---> NIT-bhopal (Vlsi - cgpa 8.59) Looking for a permanent and challenging Role in chip design / verification. TOOL FLOW EXPOSURE • Synthesis – DC • Library preparation – MWDB, LEF • QFP/BGA/Flipchip Packaging • IO Planning • Design planning/Floorplanning - ICC • Hier Physical Design - ICC • PnR flow flush/Methodology development – ICC • CTS/Multicorner CTO – ICC, • Crosstalk/DFM aware routing - ICC, • DMSA Timing analysis and ECOs – PT-SI • IR drop and EM analysis • GDSII integration, DRC, LVS, ANT, ERC Ph https://www.facebook.com/groups/vlsiforum/