/ http://www.slideshare.net/images/logo.gif / 際際滷Share feed for 際際滷shows by User: VinaySoni1 https://cdn.slidesharecdn.com/profile-photo-VinaySoni1-48x48.jpg?cb=1522973916 Experience Summary :: DFT Architecture and LBIST for SoCs Testing ==> Defination scan compression, low coverage analysis, improve test coverage for various fault models using test point insertion in the design, pattern generation and simulation with SDF, post silicon debug. SoC TEST mode STA constraint and Analysis ==> Defining TEST mode STA constraints and Analysis-Providing Physical aware ECO and Xtalk fixing along with other custom check to PD Team. For example- Single stuck-at, At-speed transition, test shift, lbist shift, lbist capture. JTAG Implementation ==> BSR insertion, pattern generation and simulation. Implementing/Defining JTAG registers for other various test modes. ... http://www.st.com