�ݺ�ߣshows by User: anandhavel

�ݺ�ߣshows by User: anandhavel / http://www.slideshare.net/images/logo.gif �ݺ�ߣshows by User: anandhavel / Thu, 30 Jan 2014 17:13:31 GMT �ݺ�ߣShare feed for �ݺ�ߣshows by User: anandhavel Honeywell_Trainee_Project_Report /slideshow/e806670-ieee-format-report/30642167 e806670ieeeformatreport-140130171331-phpapp01
• Worked under the guidance of a senior technology specialist in a highly professional environment. Created a Parts Stress Analysis (PSA) library of 2670+ components. • An estimation showed that the Reliability Maintainability System Safety (RMSS) team saved 15hrs per 100 component types in performing PSA using my parts library. • Created a reliability prediction library and time savings was found to be approximately 30 minutes for 19 components. Studied a commonly used push-pull DC-DC convertor and performed theoretical calculation for PSA. • The circuit was simulated in LTspice and OrCAD Pspice lite. The theoretical calculations and simulated values were compared and a maximum variance of 7.5% was observed. ]]>
• Worked under the guidance of a senior technology specialist in a highly professional environment. Created a Parts Stress Analysis (PSA) library of 2670+ components. • An estimation showed that the Reliability Maintainability System Safety (RMSS) team saved 15hrs per 100 component types in performing PSA using my parts library. • Created a reliability prediction library and time savings was found to be approximately 30 minutes for 19 components. Studied a commonly used push-pull DC-DC convertor and performed theoretical calculation for PSA. • The circuit was simulated in LTspice and OrCAD Pspice lite. The theoretical calculations and simulated values were compared and a maximum variance of 7.5% was observed. ]]> Thu, 30 Jan 2014 17:13:31 GMT /slideshow/e806670-ieee-format-report/30642167 anandhavel@slideshare.net(anandhavel) Honeywell_Trainee_Project_Report anandhavel • Worked under the guidance of a senior technology specialist in a highly professional environment. Created a Parts Stress Analysis (PSA) library of 2670+ components. • An estimation showed that the Reliability Maintainability System Safety (RMSS) team saved 15hrs per 100 component types in performing PSA using my parts library. • Created a reliability prediction library and time savings was found to be approximately 30 minutes for 19 components. Studied a commonly used push-pull DC-DC convertor and performed theoretical calculation for PSA. • The circuit was simulated in LTspice and OrCAD Pspice lite. The theoretical calculations and simulated values were compared and a maximum variance of 7.5% was observed. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/e806670ieeeformatreport-140130171331-phpapp01-thumbnail.jpg?width=120&height=120&fit=bounds" /><br> • Worked under the guidance of a senior technology specialist in a highly professional environment. Created a Parts Stress Analysis (PSA) library of 2670+ components. • An estimation showed that the Reliability Maintainability System Safety (RMSS) team saved 15hrs per 100 component types in performing PSA using my parts library. • Created a reliability prediction library and time savings was found to be approximately 30 minutes for 19 components. Studied a commonly used push-pull DC-DC convertor and performed theoretical calculation for PSA. • The circuit was simulated in LTspice and OrCAD Pspice lite. The theoretical calculations and simulated values were compared and a maximum variance of 7.5% was observed.

Honeywell_Trainee_Project_Report from Anandhavel Nagendra

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0 Podem_Report /slideshow/podemreport/30641876 podemreportanandhavel-140130170404-phpapp02
• Implemented a Path Oriented Decision Making (PODEM) algorithm for an Automatic Test Generator (ATG) for combinational logic circuits with re-convergent fan-out. • The generated test vectors were verified using deductive fault simulation. • The fault coverage after implementing Random Test Generator (RTG) was calculated and plotted. • The ATG, RTG and fault simulator were all written in more than 1200+ lines of code in python.]]>
• Implemented a Path Oriented Decision Making (PODEM) algorithm for an Automatic Test Generator (ATG) for combinational logic circuits with re-convergent fan-out. • The generated test vectors were verified using deductive fault simulation. • The fault coverage after implementing Random Test Generator (RTG) was calculated and plotted. • The ATG, RTG and fault simulator were all written in more than 1200+ lines of code in python.]]> Thu, 30 Jan 2014 17:04:04 GMT /slideshow/podemreport/30641876 anandhavel@slideshare.net(anandhavel) Podem_Report anandhavel • Implemented a Path Oriented Decision Making (PODEM) algorithm for an Automatic Test Generator (ATG) for combinational logic circuits with re-convergent fan-out. • The generated test vectors were verified using deductive fault simulation. • The fault coverage after implementing Random Test Generator (RTG) was calculated and plotted. • The ATG, RTG and fault simulator were all written in more than 1200+ lines of code in python. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/podemreportanandhavel-140130170404-phpapp02-thumbnail.jpg?width=120&height=120&fit=bounds" /><br> • Implemented a Path Oriented Decision Making (PODEM) algorithm for an Automatic Test Generator (ATG) for combinational logic circuits with re-convergent fan-out. • The generated test vectors were verified using deductive fault simulation. • The fault coverage after implementing Random Test Generator (RTG) was calculated and plotted. • The ATG, RTG and fault simulator were all written in more than 1200+ lines of code in python.

Podem_Report from Anandhavel Nagendra

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0 SRAM_System_Design_Report /anandhavel/ece6130-final-reportgroup12 ece6130finalreportgroup12-140130154039-phpapp01
• Designed schematics and layout for a 0.8V powered 512 bit SRAM memory system and arithmetic unit using 45nm transistor technology. Achieved functionality at a clock frequency of 1 GHz with a power dissipation of 0.9W. • Designed SRAM Cell array schematic & layout and registers using True Single-Phase Clock (TSPC) schematic. • Schematics and layout were drawn in Cadence Virtuoso using Hspice simulator. The power dissipation varied between the schematic and layout by 0.02%. ]]>
• Designed schematics and layout for a 0.8V powered 512 bit SRAM memory system and arithmetic unit using 45nm transistor technology. Achieved functionality at a clock frequency of 1 GHz with a power dissipation of 0.9W. • Designed SRAM Cell array schematic & layout and registers using True Single-Phase Clock (TSPC) schematic. • Schematics and layout were drawn in Cadence Virtuoso using Hspice simulator. The power dissipation varied between the schematic and layout by 0.02%. ]]> Thu, 30 Jan 2014 15:40:39 GMT /anandhavel/ece6130-final-reportgroup12 anandhavel@slideshare.net(anandhavel) SRAM_System_Design_Report anandhavel • Designed schematics and layout for a 0.8V powered 512 bit SRAM memory system and arithmetic unit using 45nm transistor technology. Achieved functionality at a clock frequency of 1 GHz with a power dissipation of 0.9W. • Designed SRAM Cell array schematic & layout and registers using True Single-Phase Clock (TSPC) schematic. • Schematics and layout were drawn in Cadence Virtuoso using Hspice simulator. The power dissipation varied between the schematic and layout by 0.02%. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/ece6130finalreportgroup12-140130154039-phpapp01-thumbnail.jpg?width=120&height=120&fit=bounds" /><br> • Designed schematics and layout for a 0.8V powered 512 bit SRAM memory system and arithmetic unit using 45nm transistor technology. Achieved functionality at a clock frequency of 1 GHz with a power dissipation of 0.9W. • Designed SRAM Cell array schematic & layout and registers using True Single-Phase Clock (TSPC) schematic. • Schematics and layout were drawn in Cadence Virtuoso using Hspice simulator. The power dissipation varied between the schematic and layout by 0.02%.

SRAM_System_Design_Report from Anandhavel Nagendra

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0 Mincut_Placement_Final_Report /anandhavel/mincut-final-report mincutfinalreportpublic-140130153344-phpapp01
• Implemented min cut placement algorithm with terminal propagation in C++ using more than 1000 lines of code. • Wire length was compared for benchmark circuits with up to 3000 nets for placement with and without terminal propagation. • Partitioning was performed using Fiduccia-Mattheyses algorithm. • The use of terminal propagation reduced wire length by an average of 27.8%. ]]>
• Implemented min cut placement algorithm with terminal propagation in C++ using more than 1000 lines of code. • Wire length was compared for benchmark circuits with up to 3000 nets for placement with and without terminal propagation. • Partitioning was performed using Fiduccia-Mattheyses algorithm. • The use of terminal propagation reduced wire length by an average of 27.8%. ]]> Thu, 30 Jan 2014 15:33:44 GMT /anandhavel/mincut-final-report anandhavel@slideshare.net(anandhavel) Mincut_Placement_Final_Report anandhavel • Implemented min cut placement algorithm with terminal propagation in C++ using more than 1000 lines of code. • Wire length was compared for benchmark circuits with up to 3000 nets for placement with and without terminal propagation. • Partitioning was performed using Fiduccia-Mattheyses algorithm. • The use of terminal propagation reduced wire length by an average of 27.8%. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/mincutfinalreportpublic-140130153344-phpapp01-thumbnail.jpg?width=120&height=120&fit=bounds" /><br> • Implemented min cut placement algorithm with terminal propagation in C++ using more than 1000 lines of code. • Wire length was compared for benchmark circuits with up to 3000 nets for placement with and without terminal propagation. • Partitioning was performed using Fiduccia-Mattheyses algorithm. • The use of terminal propagation reduced wire length by an average of 27.8%.

Mincut_Placement_Final_Report from Anandhavel Nagendra

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0 https://cdn.slidesharecdn.com/profile-photo-anandhavel-48x48.jpg?cb=1523181985 https://cdn.slidesharecdn.com/ss_thumbnails/e806670ieeeformatreport-140130171331-phpapp01-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/e806670-ieee-format-report/30642167 Honeywell_Trainee_Proj... https://cdn.slidesharecdn.com/ss_thumbnails/podemreportanandhavel-140130170404-phpapp02-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/podemreport/30641876 Podem_Report https://cdn.slidesharecdn.com/ss_thumbnails/ece6130finalreportgroup12-140130154039-phpapp01-thumbnail.jpg?width=320&height=320&fit=bounds anandhavel/ece6130-final-reportgroup12 SRAM_System_Design_Report