/ http://www.slideshare.net/images/logo.gif / 際際滷Share feed for 際際滷shows by User: anjaeho https://cdn.slidesharecdn.com/profile-photo-anjaeho-48x48.jpg?cb=1523631653 Good Skill : - RTL design about ISP of CIS device - DFTC, Design Compiler - Power-Compiler(UPF,Low power) - PrimeTime/PT-SI - Formality, TetraMAX(ATPG,FA) - Spyglass-DFT/Constraints - RTL design for SCAN, BIST, Digital - Image Signal Processing IP for CIS - Visible enhancement IP - Video Processing IP