/ http://www.slideshare.net/images/logo.gif / 際際滷Share feed for 際際滷shows by User: ankur28sethi https://cdn.slidesharecdn.com/profile-photo-ankur28sethi-48x48.jpg?cb=1523553302 Worked in Functional Verification and Formal Verification part of Chip Designing, with focus on compiler theory such as parsing, syntax tree and compiler optimizations. Worked on improving the quality of EDA tools through numerous bug fixes and enhancements; and in-depth testing in RTL languages such as Verilog and VHDL. Involved in many high quality, core simulator solutions for semi-conductor industry, with thorough insight of customer's expectations and our product's role.