�ݺ�ߣshows by User: dileepb

�ݺ�ߣshows by User: dileepb / http://www.slideshare.net/images/logo.gif �ݺ�ߣshows by User: dileepb / Fri, 12 Oct 2018 14:35:47 GMT �ݺ�ߣShare feed for �ݺ�ߣshows by User: dileepb Open Compute Summit Keynote 17 June 2011 /slideshow/open-compute-summit-keynote-17-june-2011/119218258 opencomputedileepb17june2011-181012143547
Server Optimization for Datacenter Efficiency]]>
Server Optimization for Datacenter Efficiency]]> Fri, 12 Oct 2018 14:35:47 GMT /slideshow/open-compute-summit-keynote-17-june-2011/119218258 dileepb@slideshare.net(dileepb) Open Compute Summit Keynote 17 June 2011 dileepb Server Optimization for Datacenter Efficiency <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/opencomputedileepb17june2011-181012143547-thumbnail.jpg?width=120&height=120&fit=bounds" /> Server Optimization for Datacenter Efficiency

Open Compute Summit Keynote 17 June 2011 from Dileep Bhandarkar

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0 Datacenter Dynamics Chicago 30 sept 2010 /slideshow/datacenter-dynamics-chicago-30-sept-2010/119217853 dcdchicago30sept2010-181012142954
Energy Efficiency in Datacenters Performance/Watt/Dollar]]>
Energy Efficiency in Datacenters Performance/Watt/Dollar]]> Fri, 12 Oct 2018 14:29:54 GMT /slideshow/datacenter-dynamics-chicago-30-sept-2010/119217853 dileepb@slideshare.net(dileepb) Datacenter Dynamics Chicago 30 sept 2010 dileepb Energy Efficiency in Datacenters Performance/Watt/Dollar <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/dcdchicago30sept2010-181012142954-thumbnail.jpg?width=120&height=120&fit=bounds" /> Energy Efficiency in Datacenters Performance/Watt/Dollar

Datacenter Dynamics Chicago 30 sept 2010 from Dileep Bhandarkar

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0 Energy Efficiency Considerations in Large Datacenters /slideshow/energy-efficiency-considerations-in-large-datacenters/119217231 datacenterefficiencyforlsi-181012142114
Datacenter E fficiency for LSI AIS Summit in 2011]]>
Datacenter E fficiency for LSI AIS Summit in 2011]]> Fri, 12 Oct 2018 14:21:14 GMT /slideshow/energy-efficiency-considerations-in-large-datacenters/119217231 dileepb@slideshare.net(dileepb) Energy Efficiency Considerations in Large Datacenters dileepb Datacenter E fficiency for LSI AIS Summit in 2011 <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/datacenterefficiencyforlsi-181012142114-thumbnail.jpg?width=120&height=120&fit=bounds" /> Datacenter E fficiency for LSI AIS Summit in 2011

Energy Efficiency Considerations in Large Datacenters from Dileep Bhandarkar

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0 Samsung cio-forum-2012 /slideshow/samsung-cioforum2012/119143160 samsung-cio-forum-2012dileepbhandarkarmicrosoft-181011195408
Microsoft Cloud Infrastructure Strategy]]>
Microsoft Cloud Infrastructure Strategy]]> Thu, 11 Oct 2018 19:54:08 GMT /slideshow/samsung-cioforum2012/119143160 dileepb@slideshare.net(dileepb) Samsung cio-forum-2012 dileepb Microsoft Cloud Infrastructure Strategy <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/samsung-cio-forum-2012dileepbhandarkarmicrosoft-181011195408-thumbnail.jpg?width=120&height=120&fit=bounds" /> Microsoft Cloud Infrastructure Strategy

Samsung cio-forum-2012 from Dileep Bhandarkar

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0 Data center-server-cooling-power-management-paper /slideshow/data-centerservercoolingpowermanagementpaper/119142862 data-center-server-cooling-power-management-paper-181011194917
Server Power and Performance Evaluation in High Temperature Environments]]>
Server Power and Performance Evaluation in High Temperature Environments]]> Thu, 11 Oct 2018 19:49:17 GMT /slideshow/data-centerservercoolingpowermanagementpaper/119142862 dileepb@slideshare.net(dileepb) Data center-server-cooling-power-management-paper dileepb Server Power and Performance Evaluation in High Temperature Environments <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/data-center-server-cooling-power-management-paper-181011194917-thumbnail.jpg?width=120&height=120&fit=bounds" /> Server Power and Performance Evaluation in High Temperature Environments

Data center-server-cooling-power-management-paper from Dileep Bhandarkar

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0 Moscow conference keynote in 2012 /slideshow/moscow-conference-keynote-in-2012/119142774 moscowconferencekeynote-181011194750
Microsoft Cloud Infrastructure]]>
Microsoft Cloud Infrastructure]]> Thu, 11 Oct 2018 19:47:50 GMT /slideshow/moscow-conference-keynote-in-2012/119142774 dileepb@slideshare.net(dileepb) Moscow conference keynote in 2012 dileepb Microsoft Cloud Infrastructure <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/moscowconferencekeynote-181011194750-thumbnail.jpg?width=120&height=120&fit=bounds" /> Microsoft Cloud Infrastructure

Moscow conference keynote in 2012 from Dileep Bhandarkar

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0 New Delhi Cloud Summit 05 26-11 /slideshow/new-delhi-cloud-summit-05-2611/119142610 newdelhicloudsummitdileepb05-26-11-181011194452
Microsoft customer event in New Delhi Cloud Datacenter Best PracticesHolistic Approach to Improving TCO & ROI, and Operational Excellence]]>
Microsoft customer event in New Delhi Cloud Datacenter Best PracticesHolistic Approach to Improving TCO & ROI, and Operational Excellence]]> Thu, 11 Oct 2018 19:44:52 GMT /slideshow/new-delhi-cloud-summit-05-2611/119142610 dileepb@slideshare.net(dileepb) New Delhi Cloud Summit 05 26-11 dileepb Microsoft customer event in New Delhi Cloud Datacenter Best Practices�Holistic Approach to Improving TCO & ROI, and Operational Excellence <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/newdelhicloudsummitdileepb05-26-11-181011194452-thumbnail.jpg?width=120&height=120&fit=bounds" /> Microsoft customer event in New Delhi Cloud Datacenter Best Practices�Holistic Approach to Improving TCO & ROI, and Operational Excellence

New Delhi Cloud Summit 05 26-11 from Dileep Bhandarkar

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0 Performance Characterization of the Pentium Pro Processor /slideshow/performance-characterization-of-the-pentium-pro-processor/119141755 hpca3-181011193322
HPCA 3 Paper In this paper, we characterize the performance of several business and technical benchmarks on a Pentium Pro processor based system. Various architectural data are collected using a performance monitoring counter tool. Results show that the Pentium Pro processor achieves significantly lower cycles per instruction than the Pentium processor due to its out of order and speculative execution, and non-blocking cache and memory system. Its higher clock frequency also contributes to even higher performance.]]>
HPCA 3 Paper In this paper, we characterize the performance of several business and technical benchmarks on a Pentium Pro processor based system. Various architectural data are collected using a performance monitoring counter tool. Results show that the Pentium Pro processor achieves significantly lower cycles per instruction than the Pentium processor due to its out of order and speculative execution, and non-blocking cache and memory system. Its higher clock frequency also contributes to even higher performance.]]> Thu, 11 Oct 2018 19:33:22 GMT /slideshow/performance-characterization-of-the-pentium-pro-processor/119141755 dileepb@slideshare.net(dileepb) Performance Characterization of the Pentium Pro Processor dileepb HPCA 3 Paper In this paper, we characterize the performance of several business and technical benchmarks on a Pentium Pro processor based system. Various architectural data are collected using a performance monitoring counter tool. Results show that the Pentium Pro processor achieves significantly lower cycles per instruction than the Pentium processor due to its out of order and speculative execution, and non-blocking cache and memory system. Its higher clock frequency also contributes to even higher performance. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/hpca3-181011193322-thumbnail.jpg?width=120&height=120&fit=bounds" /> HPCA 3 Paper In this paper, we characterize the performance of several business and technical benchmarks on a Pentium Pro processor based system. Various architectural data are collected using a performance monitoring counter tool. Results show that the Pentium Pro processor achieves significantly lower cycles per instruction than the Pentium processor due to its out of order and speculative execution, and non-blocking cache and memory system. Its higher clock frequency also contributes to even higher performance.

Performance Characterization of the Pentium Pro Processor from Dileep Bhandarkar

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0 Innovation lecture for hong kong /slideshow/innovation-lecture-for-hong-kong/119135284 innovationlectureforhongkong-181011175124
Perspectives on Innovation.]]>
Perspectives on Innovation.]]> Thu, 11 Oct 2018 17:51:24 GMT /slideshow/innovation-lecture-for-hong-kong/119135284 dileepb@slideshare.net(dileepb) Innovation lecture for hong kong dileepb Perspectives on Innovation. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/innovationlectureforhongkong-181011175124-thumbnail.jpg?width=120&height=120&fit=bounds" /> Perspectives on Innovation.

Innovation lecture for hong kong from Dileep Bhandarkar

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0 Performance from Architecture: Comparing a RISC and a CISC with Similar Hardware Organization - Dileep Bhandarkar Douglas W. Clark* /dileepb/performance-from-architecture-comparing-a-risc-and-a-cisc-with-similar-hardware-organization-dileep-bhandarkar-douglas-w-clark p310-bhandarkarasplosriscvscisc-180902180316
This is the paper that Dave Patterson referred to in his Turing Lecture. Performance comparisons across different computer architectures cannot usually separate the architectural contribution from various implementation and technology contributions to performance. This paper compares an example implementation from the RISC and CISC architectural schools (a MIPS M/2000 and a Digital VAX 8700) on nine of the ten SPEC benchmarks. The organizational similarity of these machines provides an opportunity to examine the purely architect ural advantages of RISC. The RISC approach offers, compared with VAX, many fewer cycles per instruction but somewhat more instructions per program. Using results from a software monitor on the MIPS machine and a hardware monitor on the VAX, this paper shows that the esulting advantage in cycles per program ranges from slightly under a factor of 2 to almost a factor of 4, with a geometric mean of 2,7. It also demonstrates the correlation between cycles per instruction and relative instruction count.]]>
This is the paper that Dave Patterson referred to in his Turing Lecture. Performance comparisons across different computer architectures cannot usually separate the architectural contribution from various implementation and technology contributions to performance. This paper compares an example implementation from the RISC and CISC architectural schools (a MIPS M/2000 and a Digital VAX 8700) on nine of the ten SPEC benchmarks. The organizational similarity of these machines provides an opportunity to examine the purely architect ural advantages of RISC. The RISC approach offers, compared with VAX, many fewer cycles per instruction but somewhat more instructions per program. Using results from a software monitor on the MIPS machine and a hardware monitor on the VAX, this paper shows that the esulting advantage in cycles per program ranges from slightly under a factor of 2 to almost a factor of 4, with a geometric mean of 2,7. It also demonstrates the correlation between cycles per instruction and relative instruction count.]]> Sun, 02 Sep 2018 18:03:16 GMT /dileepb/performance-from-architecture-comparing-a-risc-and-a-cisc-with-similar-hardware-organization-dileep-bhandarkar-douglas-w-clark dileepb@slideshare.net(dileepb) Performance from Architecture: Comparing a RISC and a CISC with Similar Hardware Organization - Dileep Bhandarkar Douglas W. Clark* dileepb This is the paper that Dave Patterson referred to in his Turing Lecture. Performance comparisons across different computer architectures cannot usually separate the architectural contribution from various implementation and technology contributions to performance. This paper compares an example implementation from the RISC and CISC architectural schools (a MIPS M/2000 and a Digital VAX 8700) on nine of the ten SPEC benchmarks. The organizational similarity of these machines provides an opportunity to examine the purely architect ural advantages of RISC. The RISC approach offers, compared with VAX, many fewer cycles per instruction but somewhat more instructions per program. Using results from a software monitor on the MIPS machine and a hardware monitor on the VAX, this paper shows that the esulting advantage in cycles per program ranges from slightly under a factor of 2 to almost a factor of 4, with a geometric mean of 2,7. It also demonstrates the correlation between cycles per instruction and relative instruction count. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/p310-bhandarkarasplosriscvscisc-180902180316-thumbnail.jpg?width=120&height=120&fit=bounds" /> This is the paper that Dave Patterson referred to in his Turing Lecture. Performance comparisons across different computer architectures cannot usually separate the architectural contribution from various implementation and technology contributions to performance. This paper compares an example implementation from the RISC and CISC architectural schools (a MIPS M/2000 and a Digital VAX 8700) on nine of the ten SPEC benchmarks. The organizational similarity of these machines provides an opportunity to examine the purely architect ural advantages of RISC. The RISC approach offers, compared with VAX, many fewer cycles per instruction but somewhat more instructions per program. Using results from a software monitor on the MIPS machine and a hardware monitor on the VAX, this paper shows that the esulting advantage in cycles per program ranges from slightly under a factor of 2 to almost a factor of 4, with a geometric mean of 2,7. It also demonstrates the correlation between cycles per instruction and relative instruction count.

Performance from Architecture: Comparing a RISC and a CISC with Similar Hardware Organization - Dileep Bhandarkar Douglas W. Clark* from Dileep Bhandarkar

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0 Qualcomm centriq 2400 hot chips final submission corrected /slideshow/qualcomm-centriq-2400-hot-chips-final-submission-corrected/112681182 qualcommcentriq2400hotchipsfinalsubmissioncorrected-180902170005
World's 1st 10 nm Server Chip QDT-designed custom core powering Qualcomm Centriq2400 Processor 5thgeneration custom core design Designed from the ground up to meet the needs of cloud service providers Fully ARMv8-compliant AArch64 only Supports EL3 (TrustZone) and EL2 (hypervisor) • Includes optional cryptography acceleration instructions AES, SHA1, SHA2-256 Designed for performance, optimized for power]]>
World's 1st 10 nm Server Chip QDT-designed custom core powering Qualcomm Centriq2400 Processor 5thgeneration custom core design Designed from the ground up to meet the needs of cloud service providers Fully ARMv8-compliant AArch64 only Supports EL3 (TrustZone) and EL2 (hypervisor) • Includes optional cryptography acceleration instructions AES, SHA1, SHA2-256 Designed for performance, optimized for power]]> Sun, 02 Sep 2018 17:00:05 GMT /slideshow/qualcomm-centriq-2400-hot-chips-final-submission-corrected/112681182 dileepb@slideshare.net(dileepb) Qualcomm centriq 2400 hot chips final submission corrected dileepb World's 1st 10 nm Server Chip QDT-designed custom core powering Qualcomm Centriq2400 Processor 5thgeneration custom core design Designed from the ground up to meet the needs of cloud service providers Fully ARMv8-compliant AArch64 only Supports EL3 (TrustZone) and EL2 (hypervisor) • Includes optional cryptography acceleration instructions AES, SHA1, SHA2-256 Designed for performance, optimized for power <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/qualcommcentriq2400hotchipsfinalsubmissioncorrected-180902170005-thumbnail.jpg?width=120&height=120&fit=bounds" /> World's 1st 10 nm Server Chip QDT-designed custom core powering Qualcomm Centriq2400 Processor 5thgeneration custom core design Designed from the ground up to meet the needs of cloud service providers Fully ARMv8-compliant AArch64 only Supports EL3 (TrustZone) and EL2 (hypervisor) • Includes optional cryptography acceleration instructions AES, SHA1, SHA2-256 Designed for performance, optimized for power

Qualcomm centriq 2400 hot chips final submission corrected from Dileep Bhandarkar

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0 Innovation lecture for shanghai final /slideshow/innovation-lecture-for-shanghai-final/112680764 innovationlectureforshanghaifinal-180902165440
Innovation and breakthrough forum 2017 25 March 201 Shanghai, China]]>
Innovation and breakthrough forum 2017 25 March 201 Shanghai, China]]> Sun, 02 Sep 2018 16:54:40 GMT /slideshow/innovation-lecture-for-shanghai-final/112680764 dileepb@slideshare.net(dileepb) Innovation lecture for shanghai final dileepb Innovation and breakthrough forum 2017 25 March 201 Shanghai, China <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/innovationlectureforshanghaifinal-180902165440-thumbnail.jpg?width=120&height=120&fit=bounds" /> Innovation and breakthrough forum 2017 25 March 201 Shanghai, China

Innovation lecture for shanghai final from Dileep Bhandarkar

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0 Semicon2018 dileepb /slideshow/semicon2018-dileepb/105794567 semicon2018dileepb-180713213620
�ݺ�ߣ for AI Panel at Semicon West 2018]]>
�ݺ�ߣ for AI Panel at Semicon West 2018]]> Fri, 13 Jul 2018 21:36:20 GMT /slideshow/semicon2018-dileepb/105794567 dileepb@slideshare.net(dileepb) Semicon2018 dileepb dileepb �ݺ�ߣ for AI Panel at Semicon West 2018 <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/semicon2018dileepb-180713213620-thumbnail.jpg?width=120&height=120&fit=bounds" /> �ݺ�ߣ for AI Panel at Semicon West 2018

Semicon2018 dileepb from Dileep Bhandarkar

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0 Linaro connect 2018 keynote final updated /slideshow/linaro-connect-2018-keynote-final-updated/91801304 linaroconnect2018keynotefinalupdated-180324145042
Keynote speech given in Hong Kong on 23 March 2018]]>
Keynote speech given in Hong Kong on 23 March 2018]]> Sat, 24 Mar 2018 14:50:42 GMT /slideshow/linaro-connect-2018-keynote-final-updated/91801304 dileepb@slideshare.net(dileepb) Linaro connect 2018 keynote final updated dileepb Keynote speech given in Hong Kong on 23 March 2018 <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/linaroconnect2018keynotefinalupdated-180324145042-thumbnail.jpg?width=120&height=120&fit=bounds" /> Keynote speech given in Hong Kong on 23 March 2018

Linaro connect 2018 keynote final updated from Dileep Bhandarkar

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0 Hipeac 2018 keynote Talk /slideshow/hipeac-2018-keynote-talk/86583381 hipeac2018keynotefinal-180123140352
For decades we have been able to take advantage of Moore’s Law to improve single thread performance, reduce power and cost with each generation of semiconductor technology. While technology has advanced after the end of Dennard scaling more than 10 years ago, the advances have slowed down. Server performance increases have relied on increasing core counts and power budgets. At the same time, workloads have changed in the era of cloud computing. Scale out is becoming more important than scale up. Domain specific architectures have started to emerge to improve the energy efficiency of emerging workloads like deep learning. This talk will provide a historical perspective and discuss emerging trends driving the development of modern processors.]]>
For decades we have been able to take advantage of Moore’s Law to improve single thread performance, reduce power and cost with each generation of semiconductor technology. While technology has advanced after the end of Dennard scaling more than 10 years ago, the advances have slowed down. Server performance increases have relied on increasing core counts and power budgets. At the same time, workloads have changed in the era of cloud computing. Scale out is becoming more important than scale up. Domain specific architectures have started to emerge to improve the energy efficiency of emerging workloads like deep learning. This talk will provide a historical perspective and discuss emerging trends driving the development of modern processors.]]> Tue, 23 Jan 2018 14:03:52 GMT /slideshow/hipeac-2018-keynote-talk/86583381 dileepb@slideshare.net(dileepb) Hipeac 2018 keynote Talk dileepb For decades we have been able to take advantage of Moore’s Law to improve single thread performance, reduce power and cost with each generation of semiconductor technology. While technology has advanced after the end of Dennard scaling more than 10 years ago, the advances have slowed down. Server performance increases have relied on increasing core counts and power budgets. At the same time, workloads have changed in the era of cloud computing. Scale out is becoming more important than scale up. Domain specific architectures have started to emerge to improve the energy efficiency of emerging workloads like deep learning. This talk will provide a historical perspective and discuss emerging trends driving the development of modern processors. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/hipeac2018keynotefinal-180123140352-thumbnail.jpg?width=120&height=120&fit=bounds" /> For decades we have been able to take advantage of Moore’s Law to improve single thread performance, reduce power and cost with each generation of semiconductor technology. While technology has advanced after the end of Dennard scaling more than 10 years ago, the advances have slowed down. Server performance increases have relied on increasing core counts and power budgets. At the same time, workloads have changed in the era of cloud computing. Scale out is becoming more important than scale up. Domain specific architectures have started to emerge to improve the energy efficiency of emerging workloads like deep learning. This talk will provide a historical perspective and discuss emerging trends driving the development of modern processors.

Hipeac 2018 keynote Talk from Dileep Bhandarkar

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0 Alpha memo july 1992 /slideshow/alpha-memo-july-1992/86113621 alphamemojuly1992-180113174322
My failed attempt to save DEC Alpha. Two years later Intel and HP joined forces to create Itanium.]]>
My failed attempt to save DEC Alpha. Two years later Intel and HP joined forces to create Itanium.]]> Sat, 13 Jan 2018 17:43:22 GMT /slideshow/alpha-memo-july-1992/86113621 dileepb@slideshare.net(dileepb) Alpha memo july 1992 dileepb My failed attempt to save DEC Alpha. Two years later Intel and HP joined forces to create Itanium. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/alphamemojuly1992-180113174322-thumbnail.jpg?width=120&height=120&fit=bounds" /> My failed attempt to save DEC Alpha. Two years later Intel and HP joined forces to create Itanium.

Alpha memo july 1992 from Dileep Bhandarkar

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0 China AI Summit talk 2017 /slideshow/china-ai-summit-talk-2017/80794630 chinamltalk2017updated-171014012756
Design Considerations for Energy Efficient Deep Learning in the Datacenter]]>
Design Considerations for Energy Efficient Deep Learning in the Datacenter]]> Sat, 14 Oct 2017 01:27:56 GMT /slideshow/china-ai-summit-talk-2017/80794630 dileepb@slideshare.net(dileepb) China AI Summit talk 2017 dileepb Design Considerations for Energy Efficient Deep Learning in the Datacenter <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/chinamltalk2017updated-171014012756-thumbnail.jpg?width=120&height=120&fit=bounds" /> Design Considerations for Energy Efficient Deep Learning in the Datacenter

China AI Summit talk 2017 from Dileep Bhandarkar

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0 Dileep Random Access Talk at salishan 2016 /slideshow/dileep-random-access-talk-at-salishan-2016/61470743 dileepbatsalishan2016-160428160454
What happened to Moore's Law?]]>
What happened to Moore's Law?]]> Thu, 28 Apr 2016 16:04:54 GMT /slideshow/dileep-random-access-talk-at-salishan-2016/61470743 dileepb@slideshare.net(dileepb) Dileep Random Access Talk at salishan 2016 dileepb What happened to Moore's Law? <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/dileepbatsalishan2016-160428160454-thumbnail.jpg?width=120&height=120&fit=bounds" /> What happened to Moore's Law?

Dileep Random Access Talk at salishan 2016 from Dileep Bhandarkar

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0 Risc vs cisc /dileepb/risc-vs-cisc-48454659 riscvscisc-150521204413-lva1-app6891
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Risc vs cisc from Dileep Bhandarkar

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0 Moscow conference keynote /slideshow/moscow-conference-keynote/48453218 moscowconferencekeynote-150521200714-lva1-app6892
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Moscow conference keynote from Dileep Bhandarkar

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0 https://cdn.slidesharecdn.com/profile-photo-dileepb-48x48.jpg?cb=1595529356 64 bit multi-core ARM server development. http://www.microsoft.com/presspass/exec/de/DileepBhandarkar/default.mspx https://cdn.slidesharecdn.com/ss_thumbnails/opencomputedileepb17june2011-181012143547-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/open-compute-summit-keynote-17-june-2011/119218258 Open Compute Summit Ke... https://cdn.slidesharecdn.com/ss_thumbnails/dcdchicago30sept2010-181012142954-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/datacenter-dynamics-chicago-30-sept-2010/119217853 Datacenter Dynamics Ch... https://cdn.slidesharecdn.com/ss_thumbnails/datacenterefficiencyforlsi-181012142114-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/energy-efficiency-considerations-in-large-datacenters/119217231 Energy Efficiency Cons...