際際滷shows by User: dredwanarnob / http://www.slideshare.net/images/logo.gif 際際滷shows by User: dredwanarnob / Mon, 13 Jul 2015 06:07:53 GMT 際際滷Share feed for 際際滷shows by User: dredwanarnob Vlsi presentation final /slideshow/vlsi-presentation-final/50453910 vlsipresentationfinal-150713060753-lva1-app6892
This presentation was VLSI I laboratory project, which was the most painful, yet the most satisfying, the most challenging, yet the most entertaining, the most tiresome, yet the most amusing and maybe the most memorable project of my BUET life, with the most talented mind I have ever seen, Naimul Hassan, (of course, he did almost all of the work, i just volunteered). The presentation contains only raw information about our work and the cells and schematics of Cadence, but it surely missed the enormous memories behind it -- the sleepless nights, hours and hours in front of PC, confusing simulation results, confusing errors, recursive DRC and LVS errors, and after the completion, me and Naim, hugging each other and crying with happiness. Surely this was the most memorable project of my life till now (and if I don't get VLSI II, this would be the most memorable project of my entire life). A really special thanks to Dr. A. B. M. Harun-Ur-Rashid Sir, Professor, Department of Electrical and Electronic Engineering, BUET and Kanak Datta Sir, Lecturer, Department of Electrical and Electronic Engineering, BUET, for assigning us the project in order to get a good practice of the most valuable software in the world Cadence.]]>
This presentation was VLSI I laboratory project, which was the most painful, yet the most satisfying, the most challenging, yet the most entertaining, the most tiresome, yet the most amusing and maybe the most memorable project of my BUET life, with the most talented mind I have ever seen, Naimul Hassan, (of course, he did almost all of the work, i just volunteered). The presentation contains only raw information about our work and the cells and schematics of Cadence, but it surely missed the enormous memories behind it -- the sleepless nights, hours and hours in front of PC, confusing simulation results, confusing errors, recursive DRC and LVS errors, and after the completion, me and Naim, hugging each other and crying with happiness. Surely this was the most memorable project of my life till now (and if I don't get VLSI II, this would be the most memorable project of my entire life). A really special thanks to Dr. A. B. M. Harun-Ur-Rashid Sir, Professor, Department of Electrical and Electronic Engineering, BUET and Kanak Datta Sir, Lecturer, Department of Electrical and Electronic Engineering, BUET, for assigning us the project in order to get a good practice of the most valuable software in the world Cadence.]]> Mon, 13 Jul 2015 06:07:53 GMT /slideshow/vlsi-presentation-final/50453910 dredwanarnob@slideshare.net(dredwanarnob) Vlsi presentation final dredwanarnob This presentation was VLSI I laboratory project, which was the most painful, yet the most satisfying, the most challenging, yet the most entertaining, the most tiresome, yet the most amusing and maybe the most memorable project of my BUET life, with the most talented mind I have ever seen, Naimul Hassan, (of course, he did almost all of the work, i just volunteered). The presentation contains only raw information about our work and the cells and schematics of Cadence, but it surely missed the enormous memories behind it -- the sleepless nights, hours and hours in front of PC, confusing simulation results, confusing errors, recursive DRC and LVS errors, and after the completion, me and Naim, hugging each other and crying with happiness. Surely this was the most memorable project of my life till now (and if I don't get VLSI II, this would be the most memorable project of my entire life). A really special thanks to Dr. A. B. M. Harun-Ur-Rashid Sir, Professor, Department of Electrical and Electronic Engineering, BUET and Kanak Datta Sir, Lecturer, Department of Electrical and Electronic Engineering, BUET, for assigning us the project in order to get a good practice of the most valuable software in the world Cadence. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsipresentationfinal-150713060753-lva1-app6892-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> This presentation was VLSI I laboratory project, which was the most painful, yet the most satisfying, the most challenging, yet the most entertaining, the most tiresome, yet the most amusing and maybe the most memorable project of my BUET life, with the most talented mind I have ever seen, Naimul Hassan, (of course, he did almost all of the work, i just volunteered). The presentation contains only raw information about our work and the cells and schematics of Cadence, but it surely missed the enormous memories behind it -- the sleepless nights, hours and hours in front of PC, confusing simulation results, confusing errors, recursive DRC and LVS errors, and after the completion, me and Naim, hugging each other and crying with happiness. Surely this was the most memorable project of my life till now (and if I don&#39;t get VLSI II, this would be the most memorable project of my entire life). A really special thanks to Dr. A. B. M. Harun-Ur-Rashid Sir, Professor, Department of Electrical and Electronic Engineering, BUET and Kanak Datta Sir, Lecturer, Department of Electrical and Electronic Engineering, BUET, for assigning us the project in order to get a good practice of the most valuable software in the world Cadence.
Vlsi presentation final from 爨萎爨爨爨爨酌鉦Θ 爨爨萎爨爨
]]> 721 4 https://cdn.slidesharecdn.com/ss_thumbnails/vlsipresentationfinal-150713060753-lva1-app6892-thumbnail.jpg?width=120&height=120&fit=bounds presentation Black http://activitystrea.ms/schema/1.0/post http://activitystrea.ms/schema/1.0/posted 0 Designing a uniform filter bank using multirate concept /slideshow/dsp2-final-presentation-2/50453668 dsp2final-presentation2-150713055349-lva1-app6891
This is a presentation on Designing a uniform filter bank using Multi-rate concept that was done as a part of the assignment given by our respected course teacher Dr. Md. Kamrul Hasan, professor, Department of Electrical and Electronic Engineering, BUET. We're really thankful to him to let us get a deeper insight of the concept by doing the assignment. Also special thanks to my group members as they have been very much co-operative to me to complete the assignment and present it. You all are great. (y)]]>
This is a presentation on Designing a uniform filter bank using Multi-rate concept that was done as a part of the assignment given by our respected course teacher Dr. Md. Kamrul Hasan, professor, Department of Electrical and Electronic Engineering, BUET. We're really thankful to him to let us get a deeper insight of the concept by doing the assignment. Also special thanks to my group members as they have been very much co-operative to me to complete the assignment and present it. You all are great. (y)]]> Mon, 13 Jul 2015 05:53:49 GMT /slideshow/dsp2-final-presentation-2/50453668 dredwanarnob@slideshare.net(dredwanarnob) Designing a uniform filter bank using multirate concept dredwanarnob This is a presentation on Designing a uniform filter bank using Multi-rate concept that was done as a part of the assignment given by our respected course teacher Dr. Md. Kamrul Hasan, professor, Department of Electrical and Electronic Engineering, BUET. We're really thankful to him to let us get a deeper insight of the concept by doing the assignment. Also special thanks to my group members as they have been very much co-operative to me to complete the assignment and present it. You all are great. (y) <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/dsp2final-presentation2-150713055349-lva1-app6891-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> This is a presentation on Designing a uniform filter bank using Multi-rate concept that was done as a part of the assignment given by our respected course teacher Dr. Md. Kamrul Hasan, professor, Department of Electrical and Electronic Engineering, BUET. We&#39;re really thankful to him to let us get a deeper insight of the concept by doing the assignment. Also special thanks to my group members as they have been very much co-operative to me to complete the assignment and present it. You all are great. (y)
Designing a uniform filter bank using multirate concept from 爨萎爨爨爨爨酌鉦Θ 爨爨萎爨爨
]]> 526 4 https://cdn.slidesharecdn.com/ss_thumbnails/dsp2final-presentation2-150713055349-lva1-app6891-thumbnail.jpg?width=120&height=120&fit=bounds presentation White http://activitystrea.ms/schema/1.0/post http://activitystrea.ms/schema/1.0/posted 0 https://public.slidesharecdn.com/v2/images/profile-picture.png 爨爨爨 爨爭爨 爨伍鉦Η爨鉦Π爨 爨踶爨爨 爨爨鉦Θ爭爨, 爨爨鉦爭 爨爭爨ム逗Μ爭 爨ム爨爭 爨о鉦爭爨爨 爨爨逗爭 爨爭爨迦 爨爨逗Σ爭 爨爭爨ム逗Μ爭 爨爭爨萎 爨爨鉦Μ爭 爨爨, 爨項鉦Λ 爨爭爭爭 爨爨鉦爨爭爨 爨爨鉦イ https://cdn.slidesharecdn.com/ss_thumbnails/vlsipresentationfinal-150713060753-lva1-app6892-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/vlsi-presentation-final/50453910 Vlsi presentation final https://cdn.slidesharecdn.com/ss_thumbnails/dsp2final-presentation2-150713055349-lva1-app6891-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/dsp2-final-presentation-2/50453668 Designing a uniform fi...