ºÝºÝߣshows by User: fichura / http://www.slideshare.net/images/logo.gif ºÝºÝߣshows by User: fichura / Tue, 08 May 2012 03:58:17 GMT ºÝºÝߣShare feed for ºÝºÝߣshows by User: fichura Interface Control Unit (ICU)2012 https://es.slideshare.net/slideshow/interface-control-unit-icu2012/12844115 unidaddecontroleinterfazjcra2012-120508035820-phpapp01
This paper describes the Interface Control Unit (ICU) implementation for distributed processing and acquisition systems with strict time requirements (timing errors below 1 ns), regardless the situation of accessed resource. The ICU is the interface and control processor which decouples the operation of a control or host computer, which becomes freed from the system management and control tasks. The system is controlled by means of read and write requests, which are eventually performed in an asynchronous basis and, in some cases, performed simultaneously throughout the system within a strict time margin.]]>
This paper describes the Interface Control Unit (ICU) implementation for distributed processing and acquisition systems with strict time requirements (timing errors below 1 ns), regardless the situation of accessed resource. The ICU is the interface and control processor which decouples the operation of a control or host computer, which becomes freed from the system management and control tasks. The system is controlled by means of read and write requests, which are eventually performed in an asynchronous basis and, in some cases, performed simultaneously throughout the system within a strict time margin.]]> Tue, 08 May 2012 03:58:17 GMT https://es.slideshare.net/slideshow/interface-control-unit-icu2012/12844115 fichura@slideshare.net(fichura) Interface Control Unit (ICU)2012 fichura This paper describes the Interface Control Unit (ICU) implementation for distributed processing and acquisition systems with strict time requirements (timing errors below 1 ns), regardless the situation of accessed resource. The ICU is the interface and control processor which decouples the operation of a control or host computer, which becomes freed from the system management and control tasks. The system is controlled by means of read and write requests, which are eventually performed in an asynchronous basis and, in some cases, performed simultaneously throughout the system within a strict time margin. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/unidaddecontroleinterfazjcra2012-120508035820-phpapp01-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> This paper describes the Interface Control Unit (ICU) implementation for distributed processing and acquisition systems with strict time requirements (timing errors below 1 ns), regardless the situation of accessed resource. The ICU is the interface and control processor which decouples the operation of a control or host computer, which becomes freed from the system management and control tasks. The system is controlled by means of read and write requests, which are eventually performed in an asynchronous basis and, in some cases, performed simultaneously throughout the system within a strict time margin.
from Jose Miguel Moreno Llamas
]]> 422 4 https://cdn.slidesharecdn.com/ss_thumbnails/unidaddecontroleinterfazjcra2012-120508035820-phpapp01-thumbnail.jpg?width=120&height=120&fit=bounds document Black http://activitystrea.ms/schema/1.0/post http://activitystrea.ms/schema/1.0/posted 0 Electronic SoC /slideshow/electronic-soc/9283436 presentacinlinkedinsoc-13161773697788-phpapp02-110916075236-phpapp02
Electronic SoC includes: CONTROL UNIT=&gt; FPGA Spartan6 include: MicroBlaze Microprocessor. Memory Controller Ethernet MAC Controller I/O LVDS INTERFACE Capability USB 2.0 Controller Gigabit Ethernet PHY Controller. SDRAM DDR3 Memory(128MByte – 1Gbit) Boot loader Flash Memory (16MByte – 128Mbit) Configuration SPI Flash Memory (8MByte – 64Mbit) One power supply input (4-8V 5A), with internal DC-DC converters for supplies all circuitry. JTAG and USB to SPI flash-FPGA configuration capability.]]>
Electronic SoC includes: CONTROL UNIT=&gt; FPGA Spartan6 include: MicroBlaze Microprocessor. Memory Controller Ethernet MAC Controller I/O LVDS INTERFACE Capability USB 2.0 Controller Gigabit Ethernet PHY Controller. SDRAM DDR3 Memory(128MByte – 1Gbit) Boot loader Flash Memory (16MByte – 128Mbit) Configuration SPI Flash Memory (8MByte – 64Mbit) One power supply input (4-8V 5A), with internal DC-DC converters for supplies all circuitry. JTAG and USB to SPI flash-FPGA configuration capability.]]> Fri, 16 Sep 2011 07:51:37 GMT /slideshow/electronic-soc/9283436 fichura@slideshare.net(fichura) Electronic SoC fichura Electronic SoC includes: CONTROL UNIT=&gt; FPGA Spartan6 include: MicroBlaze Microprocessor. Memory Controller Ethernet MAC Controller I/O LVDS INTERFACE Capability USB 2.0 Controller Gigabit Ethernet PHY Controller. SDRAM DDR3 Memory(128MByte – 1Gbit) Boot loader Flash Memory (16MByte – 128Mbit) Configuration SPI Flash Memory (8MByte – 64Mbit) One power supply input (4-8V 5A), with internal DC-DC converters for supplies all circuitry. JTAG and USB to SPI flash-FPGA configuration capability. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/presentacinlinkedinsoc-13161773697788-phpapp02-110916075236-phpapp02-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br> Electronic SoC includes: CONTROL UNIT=&amp;gt; FPGA Spartan6 include: MicroBlaze Microprocessor. Memory Controller Ethernet MAC Controller I/O LVDS INTERFACE Capability USB 2.0 Controller Gigabit Ethernet PHY Controller. SDRAM DDR3 Memory(128MByte – 1Gbit) Boot loader Flash Memory (16MByte – 128Mbit) Configuration SPI Flash Memory (8MByte – 64Mbit) One power supply input (4-8V 5A), with internal DC-DC converters for supplies all circuitry. JTAG and USB to SPI flash-FPGA configuration capability.
Electronic SoC from Jose Miguel Moreno Llamas
]]> 254 1 https://cdn.slidesharecdn.com/ss_thumbnails/presentacinlinkedinsoc-13161773697788-phpapp02-110916075236-phpapp02-thumbnail.jpg?width=120&height=120&fit=bounds presentation Black http://activitystrea.ms/schema/1.0/post http://activitystrea.ms/schema/1.0/posted 0 https://public.slidesharecdn.com/v2/images/profile-picture.png Con origen de la Cuenca Manchega. Puebla de Almenara https://cdn.slidesharecdn.com/ss_thumbnails/unidaddecontroleinterfazjcra2012-120508035820-phpapp01-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/interface-control-unit-icu2012/12844115 Interface Control Unit... https://cdn.slidesharecdn.com/ss_thumbnails/presentacinlinkedinsoc-13161773697788-phpapp02-110916075236-phpapp02-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/electronic-soc/9283436 Electronic SoC