/ http://www.slideshare.net/images/logo.gif / ºÝºÝߣShare feed for ºÝºÝߣshows by User: jeyakumarananthappan https://cdn.slidesharecdn.com/profile-photo-jeyakumarananthappan-48x48.jpg?cb=1522931011 • Experience in Verilog RTL based IP design, simulation, synthesis and verification • Experience in SOC integration • Experience in AMBA/I2C bus protocols, MIPI, SD/MMC protocols. • Synthesis of FPGA/ASIC designs • Gate level netlist and timing simulations • Functional pattern generation and re-simulation • FPGA/Post silicon validation • DC/RC synthesis scripts • LINT checks • Advance CDC checks • Non-Resettable flop checks • RMM guidelines and synthesis techniques • Verilog behavioral modeling Specialties: Tools:- Simulation - ModelSim, NC Sim, VCS, NC-Verilog and Aldec’s Active HDL, Synthesis - Design Compiler, RTL Compiler, Leonardo Spectrum, Synplify Pro a http://vlsicare.blogspot.com/