/ http://www.slideshare.net/images/logo.gif / 際際滷Share feed for 際際滷shows by User: manisudabathula https://public.slidesharecdn.com/v2/images/profile-picture.png Summary of Qualifications Good understanding of the ASIC and FPGA design flow Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog Very good knowledge in verification methodologies Good knowledge of Digitial Design Concepts Experience in using industry standard EDA tools for the front-end design and verification