/ http://www.slideshare.net/images/logo.gif / 際際滷Share feed for 際際滷shows by User: manoj94 https://cdn.slidesharecdn.com/profile-photo-manoj94-48x48.jpg?cb=1518420867 $ Hands on experience in designing SOC layout using Synopsys ICC in various deep sub-micron technologies with less than 45nm $ Full chip and Block level layout implementation $ Custom placement and routing for design specific requirement $ Implementing low power techniques for multi-stage domain design $ ECO (Engineering Change Order) implementation $ Timing sign-off and Physical Verification of chip $ LVS and DFM rule checks and validation for design