/ http://www.slideshare.net/images/logo.gif / 際際滷Share feed for 際際滷shows by User: manojvasanthram https://public.slidesharecdn.com/v2/images/profile-picture.png Domain Knowledge : CPU, GPU, FPU, Power Management, Low Power Design, PCB, Cloud computing, x86, Embedded System Design. Skills : Digital / Logic Design, Block level design verification & debug, UVM based Test Bench Design, Static timing analysis, Functional verification, Timing closure, Synthesis, ASIC Design Flow, Clock Gating, Power Gating. Protocols : ACPI, AXI, PCIe, DDR, USB, SDIO. Tools : VCS, Verdi, DDD, Design Compiler, Prime Time, Virtuoso, Concept HDL, PSPICE, Matlab & Simulink, Xilinx ISE. Languages: Verilog, System Verilog, UVM, C, C++, PERL.