/ http://www.slideshare.net/images/logo.gif / 際際滷Share feed for 際際滷shows by User: pateldeval24 https://cdn.slidesharecdn.com/profile-photo-pateldeval24-48x48.jpg?cb=1480499069 Physical Design : Netlist to GDSII Flow (Netlist - Floor Planning - Placement - Clock-tree Synthesis - Routing - Design Verification - GDSII), includes Library Preparation, Floor planning, IO Ring creation, Power Planning, Placement , CTS and Routing activities, Timing Closure, Static and Dynamic power EM/IR analysis, Signal EM and Crosstalk noise analysis and Physical Verification, Low power design techniques. Signal integrity,Noise Analysis, OCV Analysis, Cross Clock Domain Power Analysis (Static and Dynamic IR Drop) Synthesis. Scripting Language : PERL & TCL EDA TOOLS: =>Magma Talus =>Synopsys IC COMPILER =>Synopsys PRIMETIME =>Synopsys DC COMPILER