/ http://www.slideshare.net/images/logo.gif / ºÝºÝߣShare feed for ºÝºÝߣshows by User: ramesharam1 https://cdn.slidesharecdn.com/profile-photo-ramesharam1-48x48.jpg?cb=1532238378  Overall experience of 2.8 years in RTL Design & FPGA board design  Experience in RTL design, Microarchitecture, On-chip debugging.  Experience in writing Verilog testbench for simulating RTL design before implementing on FPGAs  Good working knowledge on Xilinx FPGA and development tools •Good Experience SOC and ARM Architecture •Excellent understanding of Protocols such as AMBA AXI4 . • good knowledge of Modelsim, Questasim tools. Familiar with Object Oriented Programming. Area of Interest: Digital System Design, VLSI Design, Embedded System Design. IP design & verification SKILL SET *** HDL’s : Verilog ===== ===== ================== EDA Tools : QuestaSim (Mentor...