�ݺ�ߣshows by User: regis

�ݺ�ߣshows by User: regis_santonja / http://www.slideshare.net/images/logo.gif �ݺ�ߣshows by User: regis_santonja / Sat, 16 Nov 2024 01:50:38 GMT �ݺ�ߣShare feed for �ݺ�ߣshows by User: regis_santonja AnaVip: a UVM_MS component to drive and monitor Analog Signals /slideshow/anavip-a-uvm_ms-component-to-drive-and-monitor-analog-signals/273347022 cdnlive2015-anavip-241116015038-6e518522
The Universal Verification Methodology (UVM) is today's most advanced verification methodology of digital integrated circuits. When extended to Mixed-Signal chips it is usually known as UVM-MS. In this context, Cadence provides a set of UVM components such as the "dms_wire" for sine-waves, and the "dms_ramp" for piece-wise linear shaped signals. However, the corresponding verilog-AMS "gaskets" are pretty basic, especially on the monitoring side. For example, the dms_wire requires the verification engineer to provide a period and a duration to sample the sine wave so that its parameters (frequency, bias and amplitude) can be extracted. As such the verification engineer needs to have a clear idea of the signals max frequency to respect Shannon's law. In practice, the user would use a high oversampling ratio so that the prameters can be extracted within a single period. However, the signal might not get sampled right at its extermums, leading to measurement errors. One can increase the sample frequency to reduce the error, but knowing by how much is not straight forward : the higher the clock frequency, the higher the precision... and the longer the simulation time. The AnaVip that we developped at Freescale within the sensor division, uses a different approach based on sampling the signal when it changes by more than a user-defined precision. By this means, the simulation is faster : the number of samples varies with the slope, the faster the slope, the more the samples and vice versa. Additionally, there is no need to know the signal's maximum frequency anymore. The AnaVip is much straight forward to setup than Cadence's components and much more flexible. AnaVip is also able to monitor piece-wise linear signals. Furthermore, depending on the user-specified precision, real analog signals, whatever their shape, can be linearized (split into a piece-wise linear signal). Each linear piece detected triggers the UVC monitor to generate the appropriate transaction back to its subscribers within the testbench. For example, a regulator's output overshoot or ripples can be captured into bursts of transactions, allowing a scoreboard to check this behavior against the regulator's specification.]]>
The Universal Verification Methodology (UVM) is today's most advanced verification methodology of digital integrated circuits. When extended to Mixed-Signal chips it is usually known as UVM-MS. In this context, Cadence provides a set of UVM components such as the "dms_wire" for sine-waves, and the "dms_ramp" for piece-wise linear shaped signals. However, the corresponding verilog-AMS "gaskets" are pretty basic, especially on the monitoring side. For example, the dms_wire requires the verification engineer to provide a period and a duration to sample the sine wave so that its parameters (frequency, bias and amplitude) can be extracted. As such the verification engineer needs to have a clear idea of the signals max frequency to respect Shannon's law. In practice, the user would use a high oversampling ratio so that the prameters can be extracted within a single period. However, the signal might not get sampled right at its extermums, leading to measurement errors. One can increase the sample frequency to reduce the error, but knowing by how much is not straight forward : the higher the clock frequency, the higher the precision... and the longer the simulation time. The AnaVip that we developped at Freescale within the sensor division, uses a different approach based on sampling the signal when it changes by more than a user-defined precision. By this means, the simulation is faster : the number of samples varies with the slope, the faster the slope, the more the samples and vice versa. Additionally, there is no need to know the signal's maximum frequency anymore. The AnaVip is much straight forward to setup than Cadence's components and much more flexible. AnaVip is also able to monitor piece-wise linear signals. Furthermore, depending on the user-specified precision, real analog signals, whatever their shape, can be linearized (split into a piece-wise linear signal). Each linear piece detected triggers the UVC monitor to generate the appropriate transaction back to its subscribers within the testbench. For example, a regulator's output overshoot or ripples can be captured into bursts of transactions, allowing a scoreboard to check this behavior against the regulator's specification.]]> Sat, 16 Nov 2024 01:50:38 GMT /slideshow/anavip-a-uvm_ms-component-to-drive-and-monitor-analog-signals/273347022 regis_santonja@slideshare.net(regis_santonja) AnaVip: a UVM_MS component to drive and monitor Analog Signals regis_santonja The Universal Verification Methodology (UVM) is today's most advanced verification methodology of digital integrated circuits. When extended to Mixed-Signal chips it is usually known as UVM-MS. In this context, Cadence provides a set of UVM components such as the "dms_wire" for sine-waves, and the "dms_ramp" for piece-wise linear shaped signals. However, the corresponding verilog-AMS "gaskets" are pretty basic, especially on the monitoring side. For example, the dms_wire requires the verification engineer to provide a period and a duration to sample the sine wave so that its parameters (frequency, bias and amplitude) can be extracted. As such the verification engineer needs to have a clear idea of the signals max frequency to respect Shannon's law. In practice, the user would use a high oversampling ratio so that the prameters can be extracted within a single period. However, the signal might not get sampled right at its extermums, leading to measurement errors. One can increase the sample frequency to reduce the error, but knowing by how much is not straight forward : the higher the clock frequency, the higher the precision... and the longer the simulation time. The AnaVip that we developped at Freescale within the sensor division, uses a different approach based on sampling the signal when it changes by more than a user-defined precision. By this means, the simulation is faster : the number of samples varies with the slope, the faster the slope, the more the samples and vice versa. Additionally, there is no need to know the signal's maximum frequency anymore. The AnaVip is much straight forward to setup than Cadence's components and much more flexible. AnaVip is also able to monitor piece-wise linear signals. Furthermore, depending on the user-specified precision, real analog signals, whatever their shape, can be linearized (split into a piece-wise linear signal). Each linear piece detected triggers the UVC monitor to generate the appropriate transaction back to its subscribers within the testbench. For example, a regulator's output overshoot or ripples can be captured into bursts of transactions, allowing a scoreboard to check this behavior against the regulator's specification. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/cdnlive2015-anavip-241116015038-6e518522-thumbnail.jpg?width=120&height=120&fit=bounds" /> The Universal Verification Methodology (UVM) is today's most advanced verification methodology of digital integrated circuits. When extended to Mixed-Signal chips it is usually known as UVM-MS. In this context, Cadence provides a set of UVM components such as the "dms_wire" for sine-waves, and the "dms_ramp" for piece-wise linear shaped signals. However, the corresponding verilog-AMS "gaskets" are pretty basic, especially on the monitoring side. For example, the dms_wire requires the verification engineer to provide a period and a duration to sample the sine wave so that its parameters (frequency, bias and amplitude) can be extracted. As such the verification engineer needs to have a clear idea of the signals max frequency to respect Shannon's law. In practice, the user would use a high oversampling ratio so that the prameters can be extracted within a single period. However, the signal might not get sampled right at its extermums, leading to measurement errors. One can increase the sample frequency to reduce the error, but knowing by how much is not straight forward : the higher the clock frequency, the higher the precision... and the longer the simulation time. The AnaVip that we developped at Freescale within the sensor division, uses a different approach based on sampling the signal when it changes by more than a user-defined precision. By this means, the simulation is faster : the number of samples varies with the slope, the faster the slope, the more the samples and vice versa. Additionally, there is no need to know the signal's maximum frequency anymore. The AnaVip is much straight forward to setup than Cadence's components and much more flexible. AnaVip is also able to monitor piece-wise linear signals. Furthermore, depending on the user-specified precision, real analog signals, whatever their shape, can be linearized (split into a piece-wise linear signal). Each linear piece detected triggers the UVC monitor to generate the appropriate transaction back to its subscribers within the testbench. For example, a regulator's output overshoot or ripples can be captured into bursts of transactions, allowing a scoreboard to check this behavior against the regulator's specification.

AnaVip: a UVM_MS component to drive and monitor Analog Signals from R辿gis SANTONJA

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0 Re usable continuous-time analog sva assertions - slides /slideshow/re-usable-continuoustime-analog-sva-assertions-slides/21520565 re-usablecontinuous-timeanalogsvaassertions-slides-130520074556-phpapp01
This paper shows how SystemVerilog Assertions (SVA) modules can be bound to analog IP blocks, shall they be at behavioral or transistor-level, enabling the assertions to become a true IP deliverable that can be reused at SoC level. It also highlights how DPIs can fix analog assertions specificities, such as getting rid of hierarchical paths, especially when probing currents. This paper also demonstrates how to flawlessly switch models between digital (wreal) and analog models without breaking the assertions. Finally, it demonstrates how one can generate an adaptive clock to continuously assert analog properties whose stability over time is critical, such as current or voltage references or supplies.]]>
This paper shows how SystemVerilog Assertions (SVA) modules can be bound to analog IP blocks, shall they be at behavioral or transistor-level, enabling the assertions to become a true IP deliverable that can be reused at SoC level. It also highlights how DPIs can fix analog assertions specificities, such as getting rid of hierarchical paths, especially when probing currents. This paper also demonstrates how to flawlessly switch models between digital (wreal) and analog models without breaking the assertions. Finally, it demonstrates how one can generate an adaptive clock to continuously assert analog properties whose stability over time is critical, such as current or voltage references or supplies.]]> Mon, 20 May 2013 07:45:56 GMT /slideshow/re-usable-continuoustime-analog-sva-assertions-slides/21520565 regis_santonja@slideshare.net(regis_santonja) Re usable continuous-time analog sva assertions - slides regis_santonja This paper shows how SystemVerilog Assertions (SVA) modules can be bound to analog IP blocks, shall they be at behavioral or transistor-level, enabling the assertions to become a true IP deliverable that can be reused at SoC level. It also highlights how DPIs can fix analog assertions specificities, such as getting rid of hierarchical paths, especially when probing currents. This paper also demonstrates how to flawlessly switch models between digital (wreal) and analog models without breaking the assertions. Finally, it demonstrates how one can generate an adaptive clock to continuously assert analog properties whose stability over time is critical, such as current or voltage references or supplies. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/re-usablecontinuous-timeanalogsvaassertions-slides-130520074556-phpapp01-thumbnail.jpg?width=120&height=120&fit=bounds" /> This paper shows how SystemVerilog Assertions (SVA) modules can be bound to analog IP blocks, shall they be at behavioral or transistor-level, enabling the assertions to become a true IP deliverable that can be reused at SoC level. It also highlights how DPIs can fix analog assertions specificities, such as getting rid of hierarchical paths, especially when probing currents. This paper also demonstrates how to flawlessly switch models between digital (wreal) and analog models without breaking the assertions. Finally, it demonstrates how one can generate an adaptive clock to continuously assert analog properties whose stability over time is critical, such as current or voltage references or supplies.

Re usable continuous-time analog sva assertions - slides from R辿gis SANTONJA

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0 Re usable continuous-time analog sva assertions /slideshow/re-usable-continuoustime-analog-sva-assertions/21520118 re-usablecontinuous-timeanalogsvaassertions-130520073933-phpapp02
This paper shows how SystemVerilog Assertions (SVA) modules can be bound to analog IP blocks, shall they be at behavioral or transistor-level, enabling the assertions to become a true IP deliverable that can be reused at SoC level. It also highlights how DPIs can fix analog assertions specificities, such as getting rid of hierarchical paths, especially when probing currents. This paper also demonstrates how to flawlessly switch models between digital (wreal) and analog models without breaking the assertions. Finally, it demonstrates how one can generate an adaptive clock to continuously assert analog properties whose stability over time is critical, such as current or voltage references or supplies.]]>
This paper shows how SystemVerilog Assertions (SVA) modules can be bound to analog IP blocks, shall they be at behavioral or transistor-level, enabling the assertions to become a true IP deliverable that can be reused at SoC level. It also highlights how DPIs can fix analog assertions specificities, such as getting rid of hierarchical paths, especially when probing currents. This paper also demonstrates how to flawlessly switch models between digital (wreal) and analog models without breaking the assertions. Finally, it demonstrates how one can generate an adaptive clock to continuously assert analog properties whose stability over time is critical, such as current or voltage references or supplies.]]> Mon, 20 May 2013 07:39:33 GMT /slideshow/re-usable-continuoustime-analog-sva-assertions/21520118 regis_santonja@slideshare.net(regis_santonja) Re usable continuous-time analog sva assertions regis_santonja This paper shows how SystemVerilog Assertions (SVA) modules can be bound to analog IP blocks, shall they be at behavioral or transistor-level, enabling the assertions to become a true IP deliverable that can be reused at SoC level. It also highlights how DPIs can fix analog assertions specificities, such as getting rid of hierarchical paths, especially when probing currents. This paper also demonstrates how to flawlessly switch models between digital (wreal) and analog models without breaking the assertions. Finally, it demonstrates how one can generate an adaptive clock to continuously assert analog properties whose stability over time is critical, such as current or voltage references or supplies. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/re-usablecontinuous-timeanalogsvaassertions-130520073933-phpapp02-thumbnail.jpg?width=120&height=120&fit=bounds" /> This paper shows how SystemVerilog Assertions (SVA) modules can be bound to analog IP blocks, shall they be at behavioral or transistor-level, enabling the assertions to become a true IP deliverable that can be reused at SoC level. It also highlights how DPIs can fix analog assertions specificities, such as getting rid of hierarchical paths, especially when probing currents. This paper also demonstrates how to flawlessly switch models between digital (wreal) and analog models without breaking the assertions. Finally, it demonstrates how one can generate an adaptive clock to continuously assert analog properties whose stability over time is critical, such as current or voltage references or supplies.

Re usable continuous-time analog sva assertions from R辿gis SANTONJA

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0 Mixed signal verification challenges - slides /slideshow/mixed-signal-verification-challenges-presentation/6518488 mixed-signalverificationchallenges-presentation-110111101139-phpapp01
Using Cadence eManager, verilog-AMS, systemverilog and Mixed-signal, mixed-level simulations to verify a sensor ASIC]]>
Using Cadence eManager, verilog-AMS, systemverilog and Mixed-signal, mixed-level simulations to verify a sensor ASIC]]> Tue, 11 Jan 2011 10:11:37 GMT /slideshow/mixed-signal-verification-challenges-presentation/6518488 regis_santonja@slideshare.net(regis_santonja) Mixed signal verification challenges - slides regis_santonja Using Cadence eManager, verilog-AMS, systemverilog and Mixed-signal, mixed-level simulations to verify a sensor ASIC <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/mixed-signalverificationchallenges-presentation-110111101139-phpapp01-thumbnail.jpg?width=120&height=120&fit=bounds" /> Using Cadence eManager, verilog-AMS, systemverilog and Mixed-signal, mixed-level simulations to verify a sensor ASIC

Mixed signal verification challenges - slides from R辿gis SANTONJA

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0 Mixed signal verification challenges /slideshow/mixed-signal-verification-challenges/6518483 mixed-signalverificationchallenges-110111101039-phpapp02
Using Cadence eManager, verilog-AMS, systemverilog and Mixed-signal, mixed-level simulations to verify a sensor ASIC]]>
Using Cadence eManager, verilog-AMS, systemverilog and Mixed-signal, mixed-level simulations to verify a sensor ASIC]]> Tue, 11 Jan 2011 10:10:34 GMT /slideshow/mixed-signal-verification-challenges/6518483 regis_santonja@slideshare.net(regis_santonja) Mixed signal verification challenges regis_santonja Using Cadence eManager, verilog-AMS, systemverilog and Mixed-signal, mixed-level simulations to verify a sensor ASIC <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/mixed-signalverificationchallenges-110111101039-phpapp02-thumbnail.jpg?width=120&height=120&fit=bounds" /> Using Cadence eManager, verilog-AMS, systemverilog and Mixed-signal, mixed-level simulations to verify a sensor ASIC

Mixed signal verification challenges from R辿gis SANTONJA

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0 Verilog Ams Used In Top Down Methodology For Wireless Integrated Circuits /slideshow/verilog-ams-used-in-top-down-methodology-for-wireless-integrated-circuits/1843640 verilogamsusedintopdownmethodologyforwirelessintegratedcircuits-12499971493658-phpapp01
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]]> Tue, 11 Aug 2009 08:30:42 GMT /slideshow/verilog-ams-used-in-top-down-methodology-for-wireless-integrated-circuits/1843640 regis_santonja@slideshare.net(regis_santonja) Verilog Ams Used In Top Down Methodology For Wireless Integrated Circuits regis_santonja <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/verilogamsusedintopdownmethodologyforwirelessintegratedcircuits-12499971493658-phpapp01-thumbnail.jpg?width=120&height=120&fit=bounds" />

Verilog Ams Used In Top Down Methodology For Wireless Integrated Circuits from R辿gis SANTONJA

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0 Cv June 2009 /regis_santonja/cv-june-2009 cvjune2009-124473469544-phpapp02
My resume]]>
My resume]]> Thu, 11 Jun 2009 10:38:49 GMT /regis_santonja/cv-june-2009 regis_santonja@slideshare.net(regis_santonja) Cv June 2009 regis_santonja My resume <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/cvjune2009-124473469544-phpapp02-thumbnail.jpg?width=120&height=120&fit=bounds" /> My resume

Cv June 2009 from R辿gis SANTONJA

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0 Mc13783 /slideshow/mc13783/1429347 mc13783-124222894267-phpapp02
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]]> Wed, 13 May 2009 10:35:56 GMT /slideshow/mc13783/1429347 regis_santonja@slideshare.net(regis_santonja) Mc13783 regis_santonja <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/mc13783-124222894267-phpapp02-thumbnail.jpg?width=120&height=120&fit=bounds" />

Mc13783 from R辿gis SANTONJA

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0 Multi Supply Digital Layout /slideshow/multisupply-digital-layout/1184774 multisupplydigitallayout-123782138128-phpapp01
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Multi Supply Digital Layout from R辿gis SANTONJA

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0 Verification Of 1 M+ Transistors Mixed Signal Ic /slideshow/verification-of-1m-transistors-mixed-signal-ic/1184312 verificationof1mtransistorsmixedsignalic-12378151753-phpapp02
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Verification Of 1 M+ Transistors Mixed Signal Ic from R辿gis SANTONJA

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0 Verification Of 1 M+ Transistors Mixed Signal Ic Presentation /regis_santonja/verification-of-1m-transistors-mixed-signal-ic-presentation verificationof1mtransistorsmixedsignalicpresentation-123781510913-phpapp01
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Verification Of 1 M+ Transistors Mixed Signal Ic Presentation from R辿gis SANTONJA

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0 https://cdn.slidesharecdn.com/profile-photo-regis_santonja-48x48.jpg?cb=1731721737 20 years experience in semiconductors (digital and analog) Mixed-signal IC verification - Advanced Mixed-Signal Verification techniques: Hybrid module-based/UVM testbench (drivers, monitors, sequencer, digital and analog parameter randomization), Metric Driven Verification, Functional coverage (mixed-signal assertions), automatic verification plan (vPlan) update (regressions), accurate Verilog-AMS and fast Wreal modeling, SystemVerilog, DPI, VPI. - Motion Sensors verification - Complex Power-Management, Audio and User interface IC (1+ million components) International Team Lead & Project Management - Multi-cultural context (US, Europe, India) - Organize tasks and plannings, priorities,... amssocverification.blogspot.fr/ https://cdn.slidesharecdn.com/ss_thumbnails/cdnlive2015-anavip-241116015038-6e518522-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/anavip-a-uvm_ms-component-to-drive-and-monitor-analog-signals/273347022 AnaVip: a UVM_MS compo... https://cdn.slidesharecdn.com/ss_thumbnails/re-usablecontinuous-timeanalogsvaassertions-slides-130520074556-phpapp01-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/re-usable-continuoustime-analog-sva-assertions-slides/21520565 Re usable continuous-t... https://cdn.slidesharecdn.com/ss_thumbnails/re-usablecontinuous-timeanalogsvaassertions-130520073933-phpapp02-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/re-usable-continuoustime-analog-sva-assertions/21520118 Re usable continuous-t...