/ http://www.slideshare.net/images/logo.gif / 際際滷Share feed for 際際滷shows by User: saikumarm7 https://cdn.slidesharecdn.com/profile-photo-saikumarm7-48x48.jpg?cb=1523445503 Having 1yr experience in Semiconductor Industry involved in the activities ranging from RTL to GDSII * Digital Design, Verilog HDL * Involved in Physical Design activities anything ranging from RTL to GDSII * Comprehensive understanding of methodologies of Floor Planning, Power Planning, PnR, Extraction, IR Drop Analysis, STA Signoff, Layout, Physical Verification (DRC, LVS, ERC, Functional Verification) and deep sub-micron issues * Expertise in Layout and Physical Verification * Expertise in STA sign-off