�ݺ�ߣshows by User: saiparan

�ݺ�ߣshows by User: saiparan / http://www.slideshare.net/images/logo.gif �ݺ�ߣshows by User: saiparan / Tue, 30 Jul 2019 22:33:26 GMT �ݺ�ߣShare feed for �ݺ�ߣshows by User: saiparan Micro-Architectural Attacks on Cyber-Physical Systems /slideshow/microarchitectural-attacks-on-cyberphysical-systems/159259107 2019-07-rtsops-190730223326
Micro-architectural attacks are specialized software attacks that target hardware. Modern high-performance computing hardware employs a variety of sophisticated microarchitectural components---multiple levels of caches, prefetchers, out-of-order speculative execution engine, etc.---to improve performance. Micro-architectural attacks target weaknesses in these microarchitectural components and many kinds of successful attacks---which leak secret, alter data, or delay execution times of the victim---have been demonstrated in recent years. As safety-critical cyber-physical systems (CPS) are increasingly relying on high-performance hardware, micro-architectural attacks on CPS are becoming a serious threat to their safety and security. In this talk, I will present examples of micro-architectural attacks in the context of CPS and discuss the challenges and potential approaches to defend against these attacks.]]>
Micro-architectural attacks are specialized software attacks that target hardware. Modern high-performance computing hardware employs a variety of sophisticated microarchitectural components---multiple levels of caches, prefetchers, out-of-order speculative execution engine, etc.---to improve performance. Micro-architectural attacks target weaknesses in these microarchitectural components and many kinds of successful attacks---which leak secret, alter data, or delay execution times of the victim---have been demonstrated in recent years. As safety-critical cyber-physical systems (CPS) are increasingly relying on high-performance hardware, micro-architectural attacks on CPS are becoming a serious threat to their safety and security. In this talk, I will present examples of micro-architectural attacks in the context of CPS and discuss the challenges and potential approaches to defend against these attacks.]]> Tue, 30 Jul 2019 22:33:26 GMT /slideshow/microarchitectural-attacks-on-cyberphysical-systems/159259107 saiparan@slideshare.net(saiparan) Micro-Architectural Attacks on Cyber-Physical Systems saiparan Micro-architectural attacks are specialized software attacks that target hardware. Modern high-performance computing hardware employs a variety of sophisticated microarchitectural components---multiple levels of caches, prefetchers, out-of-order speculative execution engine, etc.---to improve performance. Micro-architectural attacks target weaknesses in these microarchitectural components and many kinds of successful attacks---which leak secret, alter data, or delay execution times of the victim---have been demonstrated in recent years. As safety-critical cyber-physical systems (CPS) are increasingly relying on high-performance hardware, micro-architectural attacks on CPS are becoming a serious threat to their safety and security. In this talk, I will present examples of micro-architectural attacks in the context of CPS and discuss the challenges and potential approaches to defend against these attacks. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/2019-07-rtsops-190730223326-thumbnail.jpg?width=120&height=120&fit=bounds" /> Micro-architectural attacks are specialized software attacks that target hardware. Modern high-performance computing hardware employs a variety of sophisticated microarchitectural components---multiple levels of caches, prefetchers, out-of-order speculative execution engine, etc.---to improve performance. Micro-architectural attacks target weaknesses in these microarchitectural components and many kinds of successful attacks---which leak secret, alter data, or delay execution times of the victim---have been demonstrated in recent years. As safety-critical cyber-physical systems (CPS) are increasingly relying on high-performance hardware, micro-architectural attacks on CPS are becoming a serious threat to their safety and security. In this talk, I will present examples of micro-architectural attacks in the context of CPS and discuss the challenges and potential approaches to defend against these attacks.

Micro-Architectural Attacks on Cyber-Physical Systems from Heechul Yun

]]> 310 4 https://cdn.slidesharecdn.com/ss_thumbnails/2019-07-rtsops-190730223326-thumbnail.jpg?width=120&height=120&fit=bounds presentation Black http://activitystrea.ms/schema/1.0/post

http://activitystrea.ms/schema/1.0/posted

0 Protecting Real-Time GPU Kernels in Integrated CPU-GPU SoC Platforms /slideshow/protecting-realtime-gpu-kernels-in-integrated-cpugpu-soc-platforms-104996587/104996587 2018-07-ecrts-bwlock-v3-web-180709173038
Presentation slides of the following paper at ECRTS'18. Waqar Ali, Heechul Yun. "Protecting Real-Time GPU Kernels on Integrated CPU-GPU SoC Platforms." Euromicro Conference on Real-Time Systems (ECRTS), 2018 ]]>
Presentation slides of the following paper at ECRTS'18. Waqar Ali, Heechul Yun. "Protecting Real-Time GPU Kernels on Integrated CPU-GPU SoC Platforms." Euromicro Conference on Real-Time Systems (ECRTS), 2018 ]]> Mon, 09 Jul 2018 17:30:38 GMT /slideshow/protecting-realtime-gpu-kernels-in-integrated-cpugpu-soc-platforms-104996587/104996587 saiparan@slideshare.net(saiparan) Protecting Real-Time GPU Kernels in Integrated CPU-GPU SoC Platforms saiparan Presentation slides of the following paper at ECRTS'18. Waqar Ali, Heechul Yun. "Protecting Real-Time GPU Kernels on Integrated CPU-GPU SoC Platforms." Euromicro Conference on Real-Time Systems (ECRTS), 2018 <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/2018-07-ecrts-bwlock-v3-web-180709173038-thumbnail.jpg?width=120&height=120&fit=bounds" /> Presentation slides of the following paper at ECRTS'18. Waqar Ali, Heechul Yun. "Protecting Real-Time GPU Kernels on Integrated CPU-GPU SoC Platforms." Euromicro Conference on Real-Time Systems (ECRTS), 2018

Protecting Real-Time GPU Kernels in Integrated CPU-GPU SoC Platforms from Heechul Yun

]]> 487 4 https://cdn.slidesharecdn.com/ss_thumbnails/2018-07-ecrts-bwlock-v3-web-180709173038-thumbnail.jpg?width=120&height=120&fit=bounds presentation Black http://activitystrea.ms/schema/1.0/post

http://activitystrea.ms/schema/1.0/posted

0 Deterministic Memory Abstraction and Supporting Multicore System Architecture /slideshow/deterministic-memory-abstraction-and-supporting-multicore-system-architecture/104663373 2018-07-ecrts-dm-web-180707073501
Presentation slides of the following paper at ECRTS'18. Farzad Farshchi, Prathap Kumar Valsan, Renato Mancuso, Heechul Yun. "Deterministic Memory Abstraction and Supporting Multicore System Architecture." Euromicro Conference on Real-Time Systems (ECRTS), 2018 ]]>
Presentation slides of the following paper at ECRTS'18. Farzad Farshchi, Prathap Kumar Valsan, Renato Mancuso, Heechul Yun. "Deterministic Memory Abstraction and Supporting Multicore System Architecture." Euromicro Conference on Real-Time Systems (ECRTS), 2018 ]]> Sat, 07 Jul 2018 07:35:01 GMT /slideshow/deterministic-memory-abstraction-and-supporting-multicore-system-architecture/104663373 saiparan@slideshare.net(saiparan) Deterministic Memory Abstraction and Supporting Multicore System Architecture saiparan Presentation slides of the following paper at ECRTS'18. Farzad Farshchi, Prathap Kumar Valsan, Renato Mancuso, Heechul Yun. "Deterministic Memory Abstraction and Supporting Multicore System Architecture." Euromicro Conference on Real-Time Systems (ECRTS), 2018 <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/2018-07-ecrts-dm-web-180707073501-thumbnail.jpg?width=120&height=120&fit=bounds" /> Presentation slides of the following paper at ECRTS'18. Farzad Farshchi, Prathap Kumar Valsan, Renato Mancuso, Heechul Yun. "Deterministic Memory Abstraction and Supporting Multicore System Architecture." Euromicro Conference on Real-Time Systems (ECRTS), 2018

Deterministic Memory Abstraction and Supporting Multicore System Architecture from Heechul Yun

]]> 562 5 https://cdn.slidesharecdn.com/ss_thumbnails/2018-07-ecrts-dm-web-180707073501-thumbnail.jpg?width=120&height=120&fit=bounds presentation Black http://activitystrea.ms/schema/1.0/post

http://activitystrea.ms/schema/1.0/posted

0 A Simplex Architecture for �Intelligent and Safe �Unmanned Aerial Vehicles /slideshow/a-simplex-architecture-for-intelligent-and-safe-unmanned-aerial-vehicles/65325423 uavsimplex-160824160733
�ݺ�ߣs for our paper "A Simplex Architecture for Intelligent and Safe Unmanned Aerial Vehicles," published at RTCSA 2016]]>
�ݺ�ߣs for our paper "A Simplex Architecture for Intelligent and Safe Unmanned Aerial Vehicles," published at RTCSA 2016]]> Wed, 24 Aug 2016 16:07:33 GMT /slideshow/a-simplex-architecture-for-intelligent-and-safe-unmanned-aerial-vehicles/65325423 saiparan@slideshare.net(saiparan) A Simplex Architecture for �Intelligent and Safe �Unmanned Aerial Vehicles saiparan �ݺ�ߣs for our paper "A Simplex Architecture for �Intelligent and Safe �Unmanned Aerial Vehicles," published at RTCSA 2016 <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/uavsimplex-160824160733-thumbnail.jpg?width=120&height=120&fit=bounds" /> �ݺ�ߣs for our paper "A Simplex Architecture for �Intelligent and Safe �Unmanned Aerial Vehicles," published at RTCSA 2016

A Simplex Architecture for Intelligent and Safe Unmanned Aerial Vehicles from Heechul Yun

]]> 1970 6 https://cdn.slidesharecdn.com/ss_thumbnails/uavsimplex-160824160733-thumbnail.jpg?width=120&height=120&fit=bounds presentation Black http://activitystrea.ms/schema/1.0/post

http://activitystrea.ms/schema/1.0/posted

0 Taming Non-blocking Caches to Improve Isolation in Multicore Real-Time Systems /slideshow/taming-nonblocking-caches-to-improve-isolation-in-multicore-realtime-systems/60980140 taming-2016-rtas-web-160416044159
In this paper, we show that cache partitioning does not necessarily ensure predictable cache performance in modern COTS multicore platforms that use non-blocking caches to exploit memory-level-parallelism (MLP). Through carefully designed experiments using three real COTS multicore platforms (four distinct CPU architectures) and a cycleaccurate full system simulator, we show that special hardware registers in non-blocking caches, known as Miss Status Holding Registers (MSHRs), which track the status of outstanding cachemisses, can be a significant source of contention; we observe up to 21X WCET increase in a real COTS multicore platform due to MSHR contention. We propose a hardware and system software (OS) collaborative approach to efficiently eliminate MSHR contention for multicore real-time systems. Our approach includes a low-cost hardware extension that enables dynamic control of per-core MLP by the OS. Using the hardware extension, the OS scheduler then globally controls each core’s MLP in such a way that eliminates MSHR contention and maximizes overall throughput of the system. We implement the hardware extension in a cycle-accurate fullsystem simulator and the scheduler modification in Linux 3.14 kernel. We evaluate the effectiveness of our approach using a set of synthetic and macro benchmarks. In a case study, we achieve up to 19% WCET reduction (average: 13%) for a set of EEMBC benchmarks compared to a baseline cache partitioning setup.]]>
In this paper, we show that cache partitioning does not necessarily ensure predictable cache performance in modern COTS multicore platforms that use non-blocking caches to exploit memory-level-parallelism (MLP). Through carefully designed experiments using three real COTS multicore platforms (four distinct CPU architectures) and a cycleaccurate full system simulator, we show that special hardware registers in non-blocking caches, known as Miss Status Holding Registers (MSHRs), which track the status of outstanding cachemisses, can be a significant source of contention; we observe up to 21X WCET increase in a real COTS multicore platform due to MSHR contention. We propose a hardware and system software (OS) collaborative approach to efficiently eliminate MSHR contention for multicore real-time systems. Our approach includes a low-cost hardware extension that enables dynamic control of per-core MLP by the OS. Using the hardware extension, the OS scheduler then globally controls each core’s MLP in such a way that eliminates MSHR contention and maximizes overall throughput of the system. We implement the hardware extension in a cycle-accurate fullsystem simulator and the scheduler modification in Linux 3.14 kernel. We evaluate the effectiveness of our approach using a set of synthetic and macro benchmarks. In a case study, we achieve up to 19% WCET reduction (average: 13%) for a set of EEMBC benchmarks compared to a baseline cache partitioning setup.]]> Sat, 16 Apr 2016 04:41:59 GMT /slideshow/taming-nonblocking-caches-to-improve-isolation-in-multicore-realtime-systems/60980140 saiparan@slideshare.net(saiparan) Taming Non-blocking Caches to Improve Isolation in Multicore Real-Time Systems saiparan In this paper, we show that cache partitioning does not necessarily ensure predictable cache performance in modern COTS multicore platforms that use non-blocking caches to exploit memory-level-parallelism (MLP). Through carefully designed experiments using three real COTS multicore platforms (four distinct CPU architectures) and a cycleaccurate full system simulator, we show that special hardware registers in non-blocking caches, known as Miss Status Holding Registers (MSHRs), which track the status of outstanding cachemisses, can be a significant source of contention; we observe up to 21X WCET increase in a real COTS multicore platform due to MSHR contention. We propose a hardware and system software (OS) collaborative approach to efficiently eliminate MSHR contention for multicore real-time systems. Our approach includes a low-cost hardware extension that enables dynamic control of per-core MLP by the OS. Using the hardware extension, the OS scheduler then globally controls each core’s MLP in such a way that eliminates MSHR contention and maximizes overall throughput of the system. We implement the hardware extension in a cycle-accurate fullsystem simulator and the scheduler modification in Linux 3.14 kernel. We evaluate the effectiveness of our approach using a set of synthetic and macro benchmarks. In a case study, we achieve up to 19% WCET reduction (average: 13%) for a set of EEMBC benchmarks compared to a baseline cache partitioning setup. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/taming-2016-rtas-web-160416044159-thumbnail.jpg?width=120&height=120&fit=bounds" /> In this paper, we show that cache partitioning does not necessarily ensure predictable cache performance in modern COTS multicore platforms that use non-blocking caches to exploit memory-level-parallelism (MLP). Through carefully designed experiments using three real COTS multicore platforms (four distinct CPU architectures) and a cycleaccurate full system simulator, we show that special hardware registers in non-blocking caches, known as Miss Status Holding Registers (MSHRs), which track the status of outstanding cachemisses, can be a significant source of contention; we observe up to 21X WCET increase in a real COTS multicore platform due to MSHR contention. We propose a hardware and system software (OS) collaborative approach to efficiently eliminate MSHR contention for multicore real-time systems. Our approach includes a low-cost hardware extension that enables dynamic control of per-core MLP by the OS. Using the hardware extension, the OS scheduler then globally controls each core’s MLP in such a way that eliminates MSHR contention and maximizes overall throughput of the system. We implement the hardware extension in a cycle-accurate fullsystem simulator and the scheduler modification in Linux 3.14 kernel. We evaluate the effectiveness of our approach using a set of synthetic and macro benchmarks. In a case study, we achieve up to 19% WCET reduction (average: 13%) for a set of EEMBC benchmarks compared to a baseline cache partitioning setup.

Taming Non-blocking Caches to Improve Isolation in Multicore Real-Time Systems from Heechul Yun

]]> 1308 14 https://cdn.slidesharecdn.com/ss_thumbnails/taming-2016-rtas-web-160416044159-thumbnail.jpg?width=120&height=120&fit=bounds presentation 000000 http://activitystrea.ms/schema/1.0/post

http://activitystrea.ms/schema/1.0/posted

0 Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems /slideshow/parallelismaware-memory-interference-delay-analysis-for-cots-multicore-systems/50943765 heechul-2015-ecrts-web-150726182933-lva1-app6891
In modern Commercial Off-The-Shelf (COTS) multicore systems, each core can generate many parallel memory requests at a time. The processing of these parallel requests in the DRAM controller greatly affects the memory interference delay experienced by running tasks on the platform. In this paper, we present a new parallelism-aware worst-case memory interference delay analysis for COTS multicore systems. The analysis considers a COTS processor that can generate multiple outstanding requests and a COTS DRAM controller that has a separate read and write request buffer, prioritizes reads over writes, and supports out-of-order request processing. Focusing on LLC and DRAM bank partitioned systems, our analysis computes worst-case upper bounds on memory-interference delays, caused by competing memory requests. We validate our analysis on a Gem5 full-system simulator modeling a realistic COTS multicore platform, with a set of carefully designed synthetic benchmarks as well as SPEC2006 benchmarks. The evaluation results show that our analysis produces safe upper bounds in all tested benchmarks, while the current state-of-the-art analysis significantly under-estimates the delays. ]]>
In modern Commercial Off-The-Shelf (COTS) multicore systems, each core can generate many parallel memory requests at a time. The processing of these parallel requests in the DRAM controller greatly affects the memory interference delay experienced by running tasks on the platform. In this paper, we present a new parallelism-aware worst-case memory interference delay analysis for COTS multicore systems. The analysis considers a COTS processor that can generate multiple outstanding requests and a COTS DRAM controller that has a separate read and write request buffer, prioritizes reads over writes, and supports out-of-order request processing. Focusing on LLC and DRAM bank partitioned systems, our analysis computes worst-case upper bounds on memory-interference delays, caused by competing memory requests. We validate our analysis on a Gem5 full-system simulator modeling a realistic COTS multicore platform, with a set of carefully designed synthetic benchmarks as well as SPEC2006 benchmarks. The evaluation results show that our analysis produces safe upper bounds in all tested benchmarks, while the current state-of-the-art analysis significantly under-estimates the delays. ]]> Sun, 26 Jul 2015 18:29:33 GMT /slideshow/parallelismaware-memory-interference-delay-analysis-for-cots-multicore-systems/50943765 saiparan@slideshare.net(saiparan) Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems saiparan In modern Commercial Off-The-Shelf (COTS) multicore systems, each core can generate many parallel memory requests at a time. The processing of these parallel requests in the DRAM controller greatly affects the memory interference delay experienced by running tasks on the platform. In this paper, we present a new parallelism-aware worst-case memory interference delay analysis for COTS multicore systems. The analysis considers a COTS processor that can generate multiple outstanding requests and a COTS DRAM controller that has a separate read and write request buffer, prioritizes reads over writes, and supports out-of-order request processing. Focusing on LLC and DRAM bank partitioned systems, our analysis computes worst-case upper bounds on memory-interference delays, caused by competing memory requests. We validate our analysis on a Gem5 full-system simulator modeling a realistic COTS multicore platform, with a set of carefully designed synthetic benchmarks as well as SPEC2006 benchmarks. The evaluation results show that our analysis produces safe upper bounds in all tested benchmarks, while the current state-of-the-art analysis significantly under-estimates the delays. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/heechul-2015-ecrts-web-150726182933-lva1-app6891-thumbnail.jpg?width=120&height=120&fit=bounds" /> In modern Commercial Off-The-Shelf (COTS) multicore systems, each core can generate many parallel memory requests at a time. The processing of these parallel requests in the DRAM controller greatly affects the memory interference delay experienced by running tasks on the platform. In this paper, we present a new parallelism-aware worst-case memory interference delay analysis for COTS multicore systems. The analysis considers a COTS processor that can generate multiple outstanding requests and a COTS DRAM controller that has a separate read and write request buffer, prioritizes reads over writes, and supports out-of-order request processing. Focusing on LLC and DRAM bank partitioned systems, our analysis computes worst-case upper bounds on memory-interference delays, caused by competing memory requests. We validate our analysis on a Gem5 full-system simulator modeling a realistic COTS multicore platform, with a set of carefully designed synthetic benchmarks as well as SPEC2006 benchmarks. The evaluation results show that our analysis produces safe upper bounds in all tested benchmarks, while the current state-of-the-art analysis significantly under-estimates the delays.

Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems from Heechul Yun

]]> 1189 6 https://cdn.slidesharecdn.com/ss_thumbnails/heechul-2015-ecrts-web-150726182933-lva1-app6891-thumbnail.jpg?width=120&height=120&fit=bounds presentation Black http://activitystrea.ms/schema/1.0/post

http://activitystrea.ms/schema/1.0/posted

0 Improving Real-Time Performance on Multicore Platforms using MemGuard /slideshow/rtlws2013-mem-guard/27830703 rtlws2013-memguard-131102014912-phpapp01
A case-study presented at the Real-Time Linux Workshop (Oct, 2013) ]]>
A case-study presented at the Real-Time Linux Workshop (Oct, 2013) ]]> Sat, 02 Nov 2013 01:49:12 GMT /slideshow/rtlws2013-mem-guard/27830703 saiparan@slideshare.net(saiparan) Improving Real-Time Performance on Multicore Platforms using MemGuard saiparan A case-study presented at the Real-Time Linux Workshop (Oct, 2013) <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/rtlws2013-memguard-131102014912-phpapp01-thumbnail.jpg?width=120&height=120&fit=bounds" /> A case-study presented at the Real-Time Linux Workshop (Oct, 2013)

Improving Real-Time Performance on Multicore Platforms using MemGuard from Heechul Yun

]]> 1106 3 https://cdn.slidesharecdn.com/ss_thumbnails/rtlws2013-memguard-131102014912-phpapp01-thumbnail.jpg?width=120&height=120&fit=bounds presentation Black http://activitystrea.ms/schema/1.0/post

http://activitystrea.ms/schema/1.0/posted

0 MemGuard: Memory Bandwidth Reservation System for Efficient Performance Isolation in Multicore Platforms /slideshow/mem-guard-rtas13web-25212473/25212473 memguard-rtas13-web-130813120024-phpapp01
Memory bandwidth in modern multi-core platforms is highly variable for many reasons and is a big challenge in designing real-time systems as applications are increasingly becoming more memory intensive. In this work, we proposed, designed, and implemented an efﬁcient memory bandwidth reservation system, that we call MemGuard. MemGuard distinguishes memory bandwidth as two parts: guaranteed and best effort. It provides bandwidth reservation for the guaranteed bandwidth for temporal isolation, with efﬁcient reclaiming to maximally utilize the reserved bandwidth. It further improves performance by exploiting the best effort bandwidth after satisfying each core’s reserved bandwidth. MemGuard is evaluated with SPEC2006 benchmarks on a real hardware platform, and the results demonstrate that it is able to provide memory performance isolation with minimal impact on overall throughput.]]>
Memory bandwidth in modern multi-core platforms is highly variable for many reasons and is a big challenge in designing real-time systems as applications are increasingly becoming more memory intensive. In this work, we proposed, designed, and implemented an efﬁcient memory bandwidth reservation system, that we call MemGuard. MemGuard distinguishes memory bandwidth as two parts: guaranteed and best effort. It provides bandwidth reservation for the guaranteed bandwidth for temporal isolation, with efﬁcient reclaiming to maximally utilize the reserved bandwidth. It further improves performance by exploiting the best effort bandwidth after satisfying each core’s reserved bandwidth. MemGuard is evaluated with SPEC2006 benchmarks on a real hardware platform, and the results demonstrate that it is able to provide memory performance isolation with minimal impact on overall throughput.]]> Tue, 13 Aug 2013 12:00:24 GMT /slideshow/mem-guard-rtas13web-25212473/25212473 saiparan@slideshare.net(saiparan) MemGuard: Memory Bandwidth Reservation System for Efficient Performance Isolation in Multicore Platforms saiparan Memory bandwidth in modern multi-core platforms is highly variable for many reasons and is a big challenge in designing real-time systems as applications are increasingly becoming more memory intensive. In this work, we proposed, designed, and implemented an efﬁcient memory bandwidth reservation system, that we call MemGuard. MemGuard distinguishes memory bandwidth as two parts: guaranteed and best effort. It provides bandwidth reservation for the guaranteed bandwidth for temporal isolation, with efﬁcient reclaiming to maximally utilize the reserved bandwidth. It further improves performance by exploiting the best effort bandwidth after satisfying each core’s reserved bandwidth. MemGuard is evaluated with SPEC2006 benchmarks on a real hardware platform, and the results demonstrate that it is able to provide memory performance isolation with minimal impact on overall throughput. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/memguard-rtas13-web-130813120024-phpapp01-thumbnail.jpg?width=120&height=120&fit=bounds" /> Memory bandwidth in modern multi-core platforms is highly variable for many reasons and is a big challenge in designing real-time systems as applications are increasingly becoming more memory intensive. In this work, we proposed, designed, and implemented an efﬁcient memory bandwidth reservation system, that we call MemGuard. MemGuard distinguishes memory bandwidth as two parts: guaranteed and best effort. It provides bandwidth reservation for the guaranteed bandwidth for temporal isolation, with efﬁcient reclaiming to maximally utilize the reserved bandwidth. It further improves performance by exploiting the best effort bandwidth after satisfying each core’s reserved bandwidth. MemGuard is evaluated with SPEC2006 benchmarks on a real hardware platform, and the results demonstrate that it is able to provide memory performance isolation with minimal impact on overall throughput.

MemGuard: Memory Bandwidth Reservation System for Efficient Performance Isolation in Multicore Platforms from Heechul Yun

]]> 6007 6 https://cdn.slidesharecdn.com/ss_thumbnails/memguard-rtas13-web-130813120024-phpapp01-thumbnail.jpg?width=120&height=120&fit=bounds presentation 000000 http://activitystrea.ms/schema/1.0/post

http://activitystrea.ms/schema/1.0/posted

0 Memory access control in multiprocessor for real-time system with mixed criticality /saiparan/memory-access-control-in-multiprocessor-for-realtime-system-with-mixed-criticality ecrts12-heechul-slides-120717110443-phpapp02
Proposed/implemented a memory bandwidth control mechanism on Linux kernel for Multi-core systems. Described a timing analysis method based up on the proposed mechanism.]]>
Proposed/implemented a memory bandwidth control mechanism on Linux kernel for Multi-core systems. Described a timing analysis method based up on the proposed mechanism.]]> Tue, 17 Jul 2012 11:04:40 GMT /saiparan/memory-access-control-in-multiprocessor-for-realtime-system-with-mixed-criticality saiparan@slideshare.net(saiparan) Memory access control in multiprocessor for real-time system with mixed criticality saiparan Proposed/implemented a memory bandwidth control mechanism on Linux kernel for Multi-core systems. Described a timing analysis method based up on the proposed mechanism. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/ecrts12-heechul-slides-120717110443-phpapp02-thumbnail.jpg?width=120&height=120&fit=bounds" /> Proposed/implemented a memory bandwidth control mechanism on Linux kernel for Multi-core systems. Described a timing analysis method based up on the proposed mechanism.

Memory access control in multiprocessor for real-time system with mixed criticality from Heechul Yun

]]> 1254 3 https://cdn.slidesharecdn.com/ss_thumbnails/ecrts12-heechul-slides-120717110443-phpapp02-thumbnail.jpg?width=120&height=120&fit=bounds presentation 000000 http://activitystrea.ms/schema/1.0/post

http://activitystrea.ms/schema/1.0/posted

0 System-wide Energy Optimization for Multiple DVS Components and Real-time Tasks /slideshow/heechul-ecrts10web/5055550 heechul-ecrts10-web-100825151424-phpapp02
This presentation is about system-wide energy optimization for multiple-DVS components and real-time tasks. It describes a realistic energy model for embedded systems, and present a method to optimize the energy consumption. It is presented at ECRTS 2010. ]]>
This presentation is about system-wide energy optimization for multiple-DVS components and real-time tasks. It describes a realistic energy model for embedded systems, and present a method to optimize the energy consumption. It is presented at ECRTS 2010. ]]> Wed, 25 Aug 2010 15:14:18 GMT /slideshow/heechul-ecrts10web/5055550 saiparan@slideshare.net(saiparan) System-wide Energy Optimization for Multiple DVS Components and Real-time Tasks saiparan This presentation is about system-wide energy optimization for multiple-DVS components and real-time tasks. It describes a realistic energy model for embedded systems, and present a method to optimize the energy consumption. It is presented at ECRTS 2010. <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/heechul-ecrts10-web-100825151424-phpapp02-thumbnail.jpg?width=120&height=120&fit=bounds" /> This presentation is about system-wide energy optimization for multiple-DVS components and real-time tasks. It describes a realistic energy model for embedded systems, and present a method to optimize the energy consumption. It is presented at ECRTS 2010.

System-wide Energy Optimization for Multiple DVS Components and Real-time Tasks from Heechul Yun

]]> 825 2 https://cdn.slidesharecdn.com/ss_thumbnails/heechul-ecrts10-web-100825151424-phpapp02-thumbnail.jpg?width=120&height=120&fit=bounds presentation 000000 http://activitystrea.ms/schema/1.0/post

http://activitystrea.ms/schema/1.0/posted

0 https://cdn.slidesharecdn.com/profile-photo-saiparan-48x48.jpg?cb=1688983595 * OS level resource management for multicore based embedded real-time systems http://ittc.ku.edu/~heechul https://cdn.slidesharecdn.com/ss_thumbnails/2019-07-rtsops-190730223326-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/microarchitectural-attacks-on-cyberphysical-systems/159259107 Micro-Architectural At... https://cdn.slidesharecdn.com/ss_thumbnails/2018-07-ecrts-bwlock-v3-web-180709173038-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/protecting-realtime-gpu-kernels-in-integrated-cpugpu-soc-platforms-104996587/104996587 Protecting Real-Time G... https://cdn.slidesharecdn.com/ss_thumbnails/2018-07-ecrts-dm-web-180707073501-thumbnail.jpg?width=320&height=320&fit=bounds slideshow/deterministic-memory-abstraction-and-supporting-multicore-system-architecture/104663373 Deterministic Memory A...