際際滷shows by User: sonamverma14 / http://www.slideshare.net/images/logo.gif 際際滷shows by User: sonamverma14 / Wed, 03 Feb 2016 15:44:12 GMT 際際滷Share feed for 際際滷shows by User: sonamverma14 My resume /slideshow/my-resume-57836347/57836347 82b67a27-07a1-4e77-9bb8-e210e689548c-160203154412
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Wed, 03 Feb 2016 15:44:12 GMT /slideshow/my-resume-57836347/57836347 sonamverma14@slideshare.net(sonamverma14) My resume sonamverma14 <img style="border:1px solid #C3E6D8;float:right;" alt="" src="https://cdn.slidesharecdn.com/ss_thumbnails/82b67a27-07a1-4e77-9bb8-e210e689548c-160203154412-thumbnail.jpg?width=120&amp;height=120&amp;fit=bounds" /><br>
My resume from sonam verma
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https://public.slidesharecdn.com/v2/images/profile-picture.png I have completed M.tech in VLSI (ELECTRONICS) from Amity University with 8.45 CGPA. VLSI Programming Languages : VHDL, Verilog HDL, VHDL-AMS. Layout Tools : Modelsim SE 6.2b CADENCE (Virtuoso),Mentorgraphics(eldonet), Pspice, tanner. VLSI Programming Tools : Xillinx 13.1 FPGA : Spartan-3E, Vertex-5. Languages : C, Good programming concepts. Experienced in VHDL, Verilog, Xilinx Spartan FPGA programming. Expertise in Digital Design and Advanced Verification Techniques Proficient in RTL design, simulation and synthesis using Xilinx ISE, XST tools. Experienced with Xilinx EDK Platform. Experience in Simulation, Synthesis, MAP and Place & Route. Knowledgeable in Physical design flow. Knowl...