/ http://www.slideshare.net/images/logo.gif / ºÝºÝߣShare feed for ºÝºÝߣshows by User: sravyapeddireddy https://cdn.slidesharecdn.com/profile-photo-sravyapeddireddy-48x48.jpg?cb=1558694749  Involved in implementing GLN to GDS convergence for small ASIC.  Well trained in ASIC PD flow involving Design Planning, Floor Plan, Placement and routing, Extraction, Timing Closure and Physical Verification.  Experience in using tools like Synopsys (IC Compiler, PrimeTime), Mentor Graphics (Caliber, IC Studio).  Through knowledge of PD concepts like Liberty, MCMM, OCV, DFT, Blockages, CTS, Core utilization, SDC, TLU+ and Signal Integrity.  Have ability to resolve reliability issues like IR Drop Analysis, Congestion, Cross-talk, EM, Antenna effect , DFM and OPC.  Analytical skills of Pre-layout and Post-layout STA reports.  Basic awareness in scripting languages like PERL and ...