/ http://www.slideshare.net/images/logo.gif / 際際滷Share feed for 際際滷shows by User: vigneshkiruba7 https://cdn.slidesharecdn.com/profile-photo-vigneshkiruba7-48x48.jpg?cb=1523478270 I am working as a Physical Design Engineer, working in memory controller PHYs development. Involved in the block level physical design (i.e., Floor-planning, Power-planning, Placement, CTS, Routing). Experience in 28nm, 180nm technologies. Good experience in block level physical design, STA, Timing closure, Power optimization & Physical verification. So Much Interested in Low Power, High Speed Designs !!!! Specialties : CAD Tool Skills: Synopsys : ICC, StarXT, PrimeTime Cadence : Encounter Digital Implementation, Virtuoso速 Schematic & Layout Editor Design Experience: Physical Design - Synthesis, Formal Equivalence, Floor planning, Place, CTS & Route, Extra..