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Israel Israel

SystemVerilog/Simulation/Lint Guru - Looking for New Challenges - Let Me Help You!

Electronics / Computer Hardware

I am a Front-End CAD engineer in Intel Jerusalem (since 8/2005), supporting Logic Design and Functional Verification tools and methodologies, especially SystemVerilog RTL. My job is to help the design and verification engineers do their job better and more easily. This includes such items as tool support and methodology recommendations as well as training. I am the users'​ advocate. I pride myself on quick response and quality and completeness of my work. I have special expertise in the SystemVerilog language and in Front-End design and Functional Verification methodologies, and am insatiably curious to learn new things. Accellera awarded me its 2010 Technical Excellence Award for my.