 Having 1 year experience in VLSI Industry as a Physical Design Engineer.
 Expertise in Synthesis, Static timing analysis, Floor Planning, Power Planning and Placement.
 Expertise in Clock tree synthesis, Routing, Power Planning, Timing optimization, crosstalk analysis.
 Experience in IR Drop Analysis and Physical verification.
 Experience in various technologies - 90nm, 180nm.
 Knowledge in digital design concepts and CMOS technology.