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Dissertation Presentation
On
LOW-VOLTAGE LOW-DROPOUT REGULATOR
DEPARTMENT OF ELECTRONICS ENGINEERING
Prof. Sampat K.V. DEVYANI
HOD ECE 1309136702
Mrs.Sangeeta Mangesh M.Tech
ECE Dept. Adv. ECE
JSSATE – Noida JSSATE - Noida

OUTLINE
• Objective of Power Management
• Basic Idea of Linear Regulator
• Issues of Concern in LDOs
• Existing Techniques Used, Pros and Cons based on
Literature survey in Detail.
• Problem Statement
• Project Objective
• Parametric Objective
• Tool Used
• Block Diagram
• Progress Till date
• Proposed Work
• Conclusion
• Future Scope
References

POWER MANAGEMENT
• Batteries discharge “almost”
linearly with time.
• Circuits with reduced power
supply that are time
dependent operate poorly.
Optimal circuit performance
can not be obtained.
• Objective of a power
converter is to provide a
regulated output voltage.

COVENTIONAL POWER CONVERTERS
• Low drop‐out linear regulator (LDO)
• Switch‐inductor regulator (switching regulators)
• Switch‐capacitor regulator (charge pump)
TYPES:
• Different applications
• Desired efficiency and output ripple

LOW VOLTAGE LOW DROPOUT REGULATOR
The LDO act as a variable resistor that is placed between
input power source and the load in order to drop and control
the voltage applied to the load.
• Compared to DC‐DC switching regulators, LDOs are:
– Of continuous operation
– Easier to use
– Cheaper solution
– But of Lower efficiency

ISSUES OF CONCERN WITH LDO DESIGN
• Pass transistor
􀃎 load current will determine its size and thus layout
• Error amplifier
􀃎 The accuracy required by the LDO, determines the magnitude of the
open loop gain.
􀃎 Single pole architectures are recommended for better and easier
stability.
􀃎 The amp transient requirement is dependent on the stability i.e. gain
and phase margins. There is a trade‐off in making the PM high and
speed of amp. This is also true for the Gain.
􀃎 Should have high PSRR

ISSUES OF CONCERN WITH LDO DESIGN
(CONT’D)
• Bandgap voltage reference
􀃎 Should have high PSR
• Stability and speed of the feedback loop
􀃎 Should be assured under all load conditions
• Choice of the capacitors and feedback resistors (Rf1 and Rf2) .

1st HIGH PSR USING FEED FORWARD RIPPLE
CANCELLATION TECHNIQUE
MOTIVATION:
Problem:
– Supply ripples affect Analog/RF blocks
– Switching converter ripple frequencies are increasing
• Solution: LDO with good PSR at higher operating frequencies
• Challenges: Low drop‐out voltage, low quiescent current, small
area, high PSR across a wide frequency range

PSR DEGRADTION
PSR degrades at higher frequencies due to:
• Finite GBW of feed‐forward amplifier (cancellation path)
• Finite closed loop bandwidth
• Finite self inductance (ESL) of off‐chip capacitor

PROPOSED ARCHITECTURE:
FEED FORWARD RIPPLE CANCELLATION (FFRC)
LDO
• Main Idea:
– Cancellation path replicates the ripples at gate of pass transistor
– Gate‐source overdrive voltage is free of ripple

2nd CAPACITOR LESS LOW DROPOUT
VOLTAGE REGULATOR
Conventional LDOs are typically
implemented with at least one feedback
loop which is stabilized using a huge
external capacitor
LDOs is focused on removing this
external capacitor while maintaining
stability, good transient response and high
power supply rejection performance
Dominant pole
Conventional LDO Capacitor-Less LDO
Dominant pole

DESIGN CONSIDERATIONS IN CAPACITOR LESS
LDO
• Stability (light loads)
• Load Transient Response
• Power Supply Rejection

CAPACITOR LESS LDO TOPOLOGIES
• Capacitor‐less LDOs can be roughly divided into two main groups
based on the number of active loops.
• Single Loop LDOs
Have at least three gain stages to increase the loop gain
• Multiple Active Loop LDOs
Have two or more loops to enhance slew rate at the gate of the
pass transistor.

A SINGLE LOOP LDO ARCHITECTURE
Miller Compensation
Architecture [Leung03]
Q‐Reduction Architecture
[Lau07]
ωp1 << ωp2, ωp3

MULTI LOOPARCHITECTURES
1st Differentiator Architecture [Milliken07]
This topology enhances the
load transient response by
reducing the undershoots and
overshoots.
The on‐chip Miller Capacitor
is reduced a lot because of the
amplifier in the Differentiator
path and thus saving area
without sacrificing chip area.

MULTI LOOPARCHITECTURES (cont’d)
2nd Minimized‐Q & Adaptive Zero Compensation (MQ&AZC)
[H.C. Yang08 ]
This topology has the advantage of being stable at very light loads
(50μA),and phase margin of 60° maintained over entiire range.

MULTI LOOPARCHITECTURES (cont’d)
3rd Transimpedance LDO [J.J. Chen07]
This topology has the advantage of very fast response to load & line
transients

COMMON DESIGN SPECIFICATIONS WITH
COMPARATIVE STUDIES
PARAMETERS SPECIFICATIONS
Vref 1.4 V
Vin 3.0 V
Vout 2.8 V
Pass Transistor Dimensions M=2000, W=18μm and L=0.6μm
GBW (open loop) 500 kHz
RF1 /RF2 100KΩ/100KΩ
Technology 0.5μm
All the previously discussed capacitor‐less LDO architectures have
been designed using different technology processes or with different
design specifications.
• As a result, it is very difficult to compare them
• To fairly compare them the following common design specifications
are used:

PERFORMANCE SUMMARY ON COMPARISION
BASIS
*PSR results are for IL = 50mA
**Value extremely low to be measured

OTHER TECHNIQUES
• Other Existing Techniques:
– RC filtering
– Cascading LDOs
– Combined RC and cascading
– Increasing Loop Bandwidth
• Drawbacks:
– Large area consumption
– Large dropout voltage
– High power consumption
All these techniques do not provide sufficient PSR at
frequencies up to required ripple frequencies

PROBLEM STATEMENT
“Design Of Low-Voltage Low-Dropout Regulator Using
Current Splitting Technique And 90nm CMOS Technology”

WHY CURRENT SPLITTING TECHNIQUE?
On Literature Survey Basis:
• Primary switching regulators
Converts high dc voltage to low dc voltage with >90%
conversion efficiency.
Generate voltage ripples to minimize switching power loss.
Provide good PSR to suppress noise.
The drawback of these regulators are low power efficiency,
highly loaded circuits,high power consumption depends upon
load.
Inorder to overcome these drawbacks Current Splitting
Technique with OTA-EA and Low Iq is introduce which not
only provide high efficiency and low load but also
minimum area and low cost.

PROJECT OBJECTIVE
To Design a Low-Voltage Low-Dropout Regulator Using Current
Splitting Technique and 90nm CMOS Technology to achieve:
• An input of 1 V and An output of 0.85–0.5 V
• An Error Amplifier Current Splitting Technique
• Load Capacitor 1μF
• Quiscent Current upto 60 μA
• Minimum Area of 0.0041 mm Square

PARAMETRIC OBJECTIVE
• Design essential operating conditions and prameters are:
Technology (CMOS) 90 nm
Vdd/Vout (V) 1/0.85 1/0.5
Load Capacitor CL (μF) 1
RESR (ohm) 1
Max. IQ (μA) 60
Max. IOUT (mA) 100
Current Efficiency (%) 99.94 %
Load Regulation (mV/mA) 0.28 0.24
Output Variation in (mA)
@(IOUT1 – IOUT2 in mA)
28
(0-100)
24
(0-100)
Response Time TR (μs)* 0.28 0.24
PSR @ 100 kHz (dB) 48.1 >50
Area (mm Square) 0.0041

TOOL USED
• Cadence PSPICE
• Tanner 13.1

BLOCK DIAGRAM
Conceptual block diagram of proposed LDO regulator

PROGRESS
Literature survey Completed.
Survey Paper writing in Progress.
Simulation of an Inverter Circuit Using Tanner V 13.0 Tool

PROPOSED WORK
In this architecture not only minimize area (As Per Base Paper)
but also compact layout and calculation of power dissipation
and delay of the circuit inorder to get an efficient and stable
regulation with better performance is proposed.

CONCLUSION
• LDO regulator using an EA for low IQ with , high PSR of ~50
dB, freq range 100kHz, 28-mV max output variation for a 0 –
100 mA load transient, and a 99.94% current efficiency should
be achieved.
• The feasibility of LDO regulator should be verified using
Current Splitting Technique which is also helpful in compact
area of 0.0041 mm square.

FUTURE SCOPE
• Further this can be used as compact architechture for
minimum area and low Iq current applications.
• Minimum noise and Delay make this architecture a better
performer.
• This minimization not only increase system efficiency and
stability but also reduce the overall cost of the system.
• It can be use as best alternative for adaptive filtering.

REFRENCES
BASE PAPER: Chung-Hsun Huang, Member, IEEE, Ying-Ting
Ma, and Wei-Chen Liao, “Deaign of a Low – Voltage Low –
Dropout Regulator,” IEEE J. TRANSACTIONS ON VERY
LARGE SCALE INTEGRATION (VLSI) SYSTEMS , VOL. 22,
NO. 6, JUNE 2014.
[1] Y.-H. Lee, Y.-Y. Yang, K.-H. Chen, Y.-H. Lin, S.-J. Wang, K.-
L. Zheng, P.-F. Chen, C.-Y. Hsieh, Y.-Z. Ke, Y.-K. Chen, and
C.-C. Huang, “A DVS embedded system power management
for high efficiency integrated SoC in UWB system,” IEEE J.
Solid-State Circuits, vol. 45, no. 11, pp. 2227–2238, Nov.
2010.
[2] M. El-Nozahi, A. Amer, J. Torres, K. Entesari, and E.
Sanchez-Sinencio, “High PSR low drop-out regulator with
feed-forward ripple cancellation technique,” IEEE J. Solid-
State Circuits, vol. 45, no. 3, pp. 565–577, Mar. 2010.

REFRENCES
[3] P. Hazucha, T. Karnik, B. A. Bloechel, C. Parsons, D. Finan,
and S. Borkar, “Area-efficient linear regulator with ultra-fast
load regulation,” IEEE J. Solid-State Circuits, vol. 40, no. 4,
pp. 993–940, Apr. 2005.
[4] M. Al-Shyoukh, H. Lee, and R. Perez, “A transient-enhanced
low- quiescent current low-dropout regulator with buffer
impedance attenuation,” IEEE J. Solid-State Circuits, vol.
42, no. 8, pp. 1732–1742, Aug. 2007.
[5] Y.-H. Lam and W.-H. Ki, “A 0.9 V 0.35 μm adaptively
biased CMOS LDO regulator with fast transient response,” in
Proc. IEEE Int. Solid- State Circuits Conf., Feb. 2008, pp.
442–443, 626.
[6] H.-C. Lin, H.-H. Wu, and T.-Y. Chang, “An active- frequency
compensation scheme for CMOS low-dropout regulators
with transient-response improvement,” IEEE Trans.
Circuits Syst. II, Exp. Briefs, vol. 55, no. 9, pp. 853–857, Sep.
2008.

[7] A. Garimella, M. W. Rashid, and P. M. Furth, “Reverse nested
miller compensation using current Buffers in a three-stage
LDO,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no.
4, pp. 250–254, Apr. 2010
[8] C. Chen, J. H. Wu, and Z. X. Wang, “150 mA LDO with self
adjusting frequency compensation scheme,” Electron. Lett.,
vol. 47, no. 13, pp. 767–768, Jun. 2011.
[9] J. Hu, B. Hu, Y. Fan, and M. Ismail, “A 500 nA quiescent, 100
mA maximum load CMOS low-dropout regulator,” in Proc.
IEEE Int. Conf. Electron. Circuits Syst., Dec. 2011, pp. 386–
389.
[10] C. Zhan and W.-H. Ki, “An adaptively biased low-dropout
regulator with transient enhancement,” in Proc. Asia South
Pacific Design Autom. Conf., 2011, pp. 117–118.
[11] Edgar Sánchez-Sinencio, “Low Drop-Out (LDO) Linear
Regulators : Design Considerations and Trends for High
Power Supply Rejection (PSR),” IEEE Santa Clara Valley
(SCV) Solid State Circuits Society, February 2011.

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