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Lecture4 nmos process

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The document describes the fabrication process of NMOS transistors. It involves 10 main steps: 1) using a p-doped silicon substrate, 2) growing a thick silicon dioxide layer, 3) patterning using photoresist and masks to expose areas for doping, 4) doping exposed areas to form the source and drain, 5) growing a thin silicon dioxide layer, 6) depositing polysilicon and patterning it to form the gate, 7) growing contacts through another oxide layer, and 8) depositing metal to connect the gate, source and drain. The process is self-aligning and forms enhancement mode transistors, while an extra ion implantation step is needed to form depletion mode transistors that have

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1 Operation of NMOS Transistor
2 Operation of NMOS Enhancement Transistor •The action of Enhancement mode device can be explained in 3 sets of conditions. •To establish a channel , a minimum voltage level of threshold voltage Vt must be established between gate and source(gate and substrate) •Casei) Vgs>Vt Vds=0V •Channel Established •But no current flow between source and drain
3 Operation of NMOS Enhancement Transistor Caseii) Vgs>Vt Vds<Vgs-Vt •Effective gate voltage is Vg=Vgs-Vt •Voltage available to invert the channel at drain end •The device is in non saturation region of operation •Current flows from drain to source
4 Operation of NMOS Enhancement Transistor Caseiii) Vgs>Vt Vds Vgs-Vt •Over the part of the channel, near drain, there is insufficient electric field available to give rise to an inversion layer to create the channel. •The channel is therefore pinched off •Diffusion current completes the path from source to drain, causing the channel to exhibit a high resistance and behaves as a constant current source
5 Operation of NMOS Enhancement Transistor •In all cases, the channel will cease to exist and no current will flow when Vgs<Vt. •Typically for enhancement transistor Vt=0.2VDD Depletion transistor action •Channel is established due to the implant, even when Vgs<0 •This cause the channel to cease to exist a negative voltage Vtd must be applied between gate and source •Vtd is typically<-0.8VDD, depending on the implant and substrate bias.
6 Operation of NMOS Enhancement Transistor
7 Circuit symbols of MOS transistors
8 NMOS Fabrication Process
9 •NMOS Process steps-Enhancement transistor •Step1: Substrate •Step 2 : Thick Oxide •Step 3: Photo resist •Step 4: Exposing to UV light through mask •Step 5: Etching the Oxide layer •Step 6: Thin Oxide •Step 7: Patterning Poly •Step 8: N Diffusion •Step 9: Contact cuts •Step 10: Metallization •NMOS Process steps-Depletion transistor •Extra process step for channel formation NMOS Fabrication Process- Contents
10 NMOS Fabrication Process-Plan •What to be fabricated? •Gate-Poly Silicon •Source-N-Diffusion •Drain- n-Diffusion •Metal contacts- Any metal (Aluminium) •Where to be fabricated? •Gate- Middle of the substrate •Source, Drain- Both sides of the Gate •Metal Contacts- Gate, Source, Drain
11 NMOS Fabrication Process Step1: Substrate Processing is carried on single crystal silicon of high purity on which required P impurities are introduced as crystal is grown. Size of wafers: 75mm to 150mm diameter and 0.4mm thick Doping concentration: Silicon Substrate
12 Step 2 : Thick Oxide A layer of SiO2 typically 1μm thick is grown all over the surface of the wafer to protect the surface. NMOS Fabrication Process P-Substrate SiO2
13 Step 3: Photo resist The surface is now covered with the photo resist which is deposited onto the wafer and spun to an even distribution of the required thickness. P-Substrate SiO2 Photo resist NMOS Fabrication Process
14 Step 4: Exposing to UV light through mask The photo resist layer is then exposed to ultraviolet light through masking which defines those regions into which diffusion is to take place together with transistor channels. P- Substrate SiO2 Photo resist UV light Optical mask NMOS Fabrication Process
15 Step 5: Etching the Oxide layer These areas are subsequently readily etched away together with the underlying SiO2 so that the wafer surface is exposed in the window defined by the mask. P-Substrate SiO2 Hardened Photo resist Hydrofluoric acid (HF) NMOS Fabrication Process
16 Step 5: After the etching process- Window in Oxide P-Substrate SiO2 Window in Oxide NMOS Fabrication Process
17 Step 6: Thin Oxide A thin layer of SiO2 (0.1μm typical) is grown over the entire chip surface P- Substrate SiO2 Thinox NMOS Fabrication Process
18 Step 7: Patterning Poly Polysilicon is deposited on the top of this to form the gate structure. The polysilicon layer consists of heavily doped polysilicon deposited by chemical vapour deposition (CVD). Thickness of poly is 1-2μm. NMOS Fabrication Process Thinox Poly Silicon P-Substrate SiO2
19 Oxidation Photo lithography Etching Diffusion/ Ion implantation NMOS Fabrication Process
20 Silicon Substrate Step 7: Further photo resist coating and masking allows the poly silicon to be patterned and then the thin oxide is removed to expose areas into which n-type impurities are to be diffused to form the source and drain. P-Substrate Poly SiliconThin oxide Thick oxide NMOS Fabrication Process
21 Step 8: N Diffusion Diffusion is achieved by heating the wafer to a high temperature and passing a gas containing the desired n-type impurity. Depth of n- diffusion is 1μm. Self Aligning: The poly silicon with underlying thin oxide and the thick oxide acts as mask during diffusion the process is self aligning. NMOS Fabrication Process P-Substrate N diffusion Depletion layer Thin oxide Thick oxide Poly Silicon
22 Step 9: Contact cuts Thick oxide (SiO2) is grown over all again and is then masked with photo resist and etched to expose selected areas of the poly silicon gate and the drain and source areas where connections are to be made. NMOS Fabrication Process P-Substrate N diffusion Depletion layer Thin oxide Thick oxide Poly Silicon
23 Step 10: Metallization The whole chip then has metal (aluminium) deposited over its surface to a thickness typically of 1μm. This metal layer is then masked and etched to form the required interconnection pattern. NMOS Fabrication Process P-Substrate Metal Contacts Thick Oxide Poly Si Thin Oxide N diffusion
24 Process steps - NMOS Depletion transistor Extra step: Ion Implantation After the step 5, i.e., after the formation of window in oxide, ion implantation must be done. All the remaining steps are same as enhancement transistor P-Substrate SiO2 Window in Oxide Ion implantation
25 NMOS Depletion transistor NMOS Depletion transistor, after all processing steps P-Substrate Metal Contacts Thick Oxide Poly Si Thin Oxide N diffusion Channel
26 Summary of NMOS Process •Processing takes place on p-doped crystal wafer on which is grown a ‘thick layer of SiO2 •Mask-1: Pattern SiO2 to expose the silicon surface in areas where paths in the diffusion layer or gate areas of transistor are required. Deposit thin oxide overall. For this reason the mask is often known as ‘thinox’ mask. Sometimes it is also called as the ‘diffusion’ mask •Mask-2: Pattern the ion implantation within the thinox region where depletion mode devices are to be produced-Self aligning
27 •Mask-3: Deposit polysilicon overall, then pattern using mask3. using the same mask, remove the thin oxide layer, where it is not covered by polysilicon. Diffuse N+ regions into areas where thin oxide has been removed. Transistor drain and sources are thus self aligning with respect to the gate structures •Mask-4: Grow thick oxide over all and then etch for contact cuts •Mask-5: Deposit metal and pattern with Mask-5 •Mask-6: would be required for the over glassing process step Summary of NMOS Process

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Lecture4 nmos process

  • 1. 1 Operation of NMOS Transistor
  • 2. 2 Operation of NMOS Enhancement Transistor •The action of Enhancement mode device can be explained in 3 sets of conditions. •To establish a channel , a minimum voltage level of threshold voltage Vt must be established between gate and source(gate and substrate) •Casei) Vgs>Vt Vds=0V •Channel Established •But no current flow between source and drain
  • 3. 3 Operation of NMOS Enhancement Transistor Caseii) Vgs>Vt Vds<Vgs-Vt •Effective gate voltage is Vg=Vgs-Vt •Voltage available to invert the channel at drain end •The device is in non saturation region of operation •Current flows from drain to source
  • 4. 4 Operation of NMOS Enhancement Transistor Caseiii) Vgs>Vt Vds Vgs-Vt •Over the part of the channel, near drain, there is insufficient electric field available to give rise to an inversion layer to create the channel. •The channel is therefore pinched off •Diffusion current completes the path from source to drain, causing the channel to exhibit a high resistance and behaves as a constant current source
  • 5. 5 Operation of NMOS Enhancement Transistor •In all cases, the channel will cease to exist and no current will flow when Vgs<Vt. •Typically for enhancement transistor Vt=0.2VDD Depletion transistor action •Channel is established due to the implant, even when Vgs<0 •This cause the channel to cease to exist a negative voltage Vtd must be applied between gate and source •Vtd is typically<-0.8VDD, depending on the implant and substrate bias.
  • 6. 6 Operation of NMOS Enhancement Transistor
  • 7. 7 Circuit symbols of MOS transistors
  • 9. 9 •NMOS Process steps-Enhancement transistor •Step1: Substrate •Step 2 : Thick Oxide •Step 3: Photo resist •Step 4: Exposing to UV light through mask •Step 5: Etching the Oxide layer •Step 6: Thin Oxide •Step 7: Patterning Poly •Step 8: N Diffusion •Step 9: Contact cuts •Step 10: Metallization •NMOS Process steps-Depletion transistor •Extra process step for channel formation NMOS Fabrication Process- Contents
  • 10. 10 NMOS Fabrication Process-Plan •What to be fabricated? •Gate-Poly Silicon •Source-N-Diffusion •Drain- n-Diffusion •Metal contacts- Any metal (Aluminium) •Where to be fabricated? •Gate- Middle of the substrate •Source, Drain- Both sides of the Gate •Metal Contacts- Gate, Source, Drain
  • 11. 11 NMOS Fabrication Process Step1: Substrate Processing is carried on single crystal silicon of high purity on which required P impurities are introduced as crystal is grown. Size of wafers: 75mm to 150mm diameter and 0.4mm thick Doping concentration: Silicon Substrate
  • 12. 12 Step 2 : Thick Oxide A layer of SiO2 typically 1μm thick is grown all over the surface of the wafer to protect the surface. NMOS Fabrication Process P-Substrate SiO2
  • 13. 13 Step 3: Photo resist The surface is now covered with the photo resist which is deposited onto the wafer and spun to an even distribution of the required thickness. P-Substrate SiO2 Photo resist NMOS Fabrication Process
  • 14. 14 Step 4: Exposing to UV light through mask The photo resist layer is then exposed to ultraviolet light through masking which defines those regions into which diffusion is to take place together with transistor channels. P- Substrate SiO2 Photo resist UV light Optical mask NMOS Fabrication Process
  • 15. 15 Step 5: Etching the Oxide layer These areas are subsequently readily etched away together with the underlying SiO2 so that the wafer surface is exposed in the window defined by the mask. P-Substrate SiO2 Hardened Photo resist Hydrofluoric acid (HF) NMOS Fabrication Process
  • 16. 16 Step 5: After the etching process- Window in Oxide P-Substrate SiO2 Window in Oxide NMOS Fabrication Process
  • 17. 17 Step 6: Thin Oxide A thin layer of SiO2 (0.1μm typical) is grown over the entire chip surface P- Substrate SiO2 Thinox NMOS Fabrication Process
  • 18. 18 Step 7: Patterning Poly Polysilicon is deposited on the top of this to form the gate structure. The polysilicon layer consists of heavily doped polysilicon deposited by chemical vapour deposition (CVD). Thickness of poly is 1-2μm. NMOS Fabrication Process Thinox Poly Silicon P-Substrate SiO2
  • 20. 20 Silicon Substrate Step 7: Further photo resist coating and masking allows the poly silicon to be patterned and then the thin oxide is removed to expose areas into which n-type impurities are to be diffused to form the source and drain. P-Substrate Poly SiliconThin oxide Thick oxide NMOS Fabrication Process
  • 21. 21 Step 8: N Diffusion Diffusion is achieved by heating the wafer to a high temperature and passing a gas containing the desired n-type impurity. Depth of n- diffusion is 1μm. Self Aligning: The poly silicon with underlying thin oxide and the thick oxide acts as mask during diffusion the process is self aligning. NMOS Fabrication Process P-Substrate N diffusion Depletion layer Thin oxide Thick oxide Poly Silicon
  • 22. 22 Step 9: Contact cuts Thick oxide (SiO2) is grown over all again and is then masked with photo resist and etched to expose selected areas of the poly silicon gate and the drain and source areas where connections are to be made. NMOS Fabrication Process P-Substrate N diffusion Depletion layer Thin oxide Thick oxide Poly Silicon
  • 23. 23 Step 10: Metallization The whole chip then has metal (aluminium) deposited over its surface to a thickness typically of 1μm. This metal layer is then masked and etched to form the required interconnection pattern. NMOS Fabrication Process P-Substrate Metal Contacts Thick Oxide Poly Si Thin Oxide N diffusion
  • 24. 24 Process steps - NMOS Depletion transistor Extra step: Ion Implantation After the step 5, i.e., after the formation of window in oxide, ion implantation must be done. All the remaining steps are same as enhancement transistor P-Substrate SiO2 Window in Oxide Ion implantation
  • 25. 25 NMOS Depletion transistor NMOS Depletion transistor, after all processing steps P-Substrate Metal Contacts Thick Oxide Poly Si Thin Oxide N diffusion Channel
  • 26. 26 Summary of NMOS Process •Processing takes place on p-doped crystal wafer on which is grown a ‘thick layer of SiO2 •Mask-1: Pattern SiO2 to expose the silicon surface in areas where paths in the diffusion layer or gate areas of transistor are required. Deposit thin oxide overall. For this reason the mask is often known as ‘thinox’ mask. Sometimes it is also called as the ‘diffusion’ mask •Mask-2: Pattern the ion implantation within the thinox region where depletion mode devices are to be produced-Self aligning
  • 27. 27 •Mask-3: Deposit polysilicon overall, then pattern using mask3. using the same mask, remove the thin oxide layer, where it is not covered by polysilicon. Diffuse N+ regions into areas where thin oxide has been removed. Transistor drain and sources are thus self aligning with respect to the gate structures •Mask-4: Grow thick oxide over all and then etch for contact cuts •Mask-5: Deposit metal and pattern with Mask-5 •Mask-6: would be required for the over glassing process step Summary of NMOS Process