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Low dropout regulator(ldo)

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This document describes the design of a low dropout voltage regulator (LDO) circuit. It includes the goals of providing a 3.3V output voltage from a 5V input. The key components of an LDO - pass transistor, error amplifier, and voltage reference - are discussed. Calculations are shown for efficiency, transistor sizes, setting the bias voltage, and sizing additional transistors. A block diagram and final schematic are presented. Post-layout simulations demonstrate the line regulation as the input voltage is changed.

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ECE5590 AN Low Dropout Regulator(LDO) -Aadit Modi(ID#16037399) -Altaf Hirani (ID#12197304)
LDO ? Linear Voltage DC regulators. ? Regulation maintained with small differences. ? Output current in range of 50-100mA. ? Pass transistor, error amplifier and voltage reference. ? Low quiescent current.
?Design a low dropout voltage regulator to provide an output voltage of 3.3V. Goals:
For the calculations we assume the following constants: ? - Pass transistor current = 1mA ? - Vout = 3.3V ? - Dropout voltage ? - VDD=5V
Block Diagram ? Pass transistor & error amplifier.
CALCULATIONS: Efficiency calculation Iq (quiescent current) = 112 uA Io (output current) = 1.39 mA Vo (output voltage) = 3.37 V Vi (input voltage) = 5 V Eff. = Io*Vo/(Io + Iq)*Vi x 100 Using the above equation yields and efficiency of about 61.1%.
- Summary of calculated transistor sizes vs the transistor simulation sizes TransistTor Calculated Size Actual Size Used Width(?m) Length(?m) Width(?m) Length(?m) M1 100 0.6 100.05 0.6 M2 100 0.6 100.05 0.6 M3 50 0.6 49.95 0.6 M4 50 0.6 49.95 0.6 M5 20 0.6 19.95 0.6 M6 250 0.6 250 0.6 TRANSISTOR SIZE TABLE
Final Schematic
Typical LDO Circuit
Calculations: - Calculation of a range of Vbias1 1. To find Ibias1: From the desired a photodiode range, the minimum value of Ibias1: VGS3 =Vphmin Ibias1 = ? K1(W/L)3 (VGS3 -VTHN )2 = ? * 50 * 10-6 A/V2 * 3?m/0.6?m * (0.8V ¨C 0.617)2 = 4.186?A =4?A The maximum value of Ibias1: Ibias1 = ? K1(W/L)3 (VGS3 -VTHN )2 = ? * 50 * 10-6 A/V2 * 3?m/0.6?m * (3.0V ¨C 0.617)2 =0.7mA
Calculations: - Calculation of sizes of the transistors M5, M4 1. To determine W5 From requirement to keep M5 in saturation region: VTH ¡ÜVGS5 = Vbias1(min) + VTHp ¨C Vph (max) = 2.8V +0.9V ¨C 3.0V = 0.7V W5 = (2InL5 )/(K1 (VGS5 -VTHN )2 ) = (2 * 1.2?A * 0.6?m)/(50?A/V2 * (0.7V ¨C 0.617V)2 ) = 4?m
Calculations: - Calculation of sizes of the transistors M5, M4 2. To determine W4 VDS4 ¡ÝVGS4 ¨C VTHN VDS4 = Vph (min) = 0.8V Assumed VGS4 = 0.75V W4 = (2InL4 )/(K1 (VGS4 -VTHN )2 ) = (2 * 1.2?A * 0.6?m)/(50?A/V2 * (0.75V ¨C 0.617V)2 ) = 1.60?m
Calculations: - Calculation of the gain for the current mirror transistors M1, M2, M7 1. To find VGS for M1, M2, M7 VGS1 = VDS1 = VGS2 = VGS1 = ¡Ì[(2Iout)/(K2 (W/L)2,7 ] + VTHp = ¡Ì(2 * 1.2?A)/(25?A/V2 * (20/2.4)) + 0.915V = 0.107V + 0.915V = 1V
Calculations: - Calculation of the gain for the current mirror transistors M1, M2, M7 2. To find VDS for current mirror: Next we find VDS2 and VDS7 (which are the same in value) VDS2,7 = VDD ¨C VDS6 = VDD - ¡Ì[(2Iout)/(K1 (W/L)6 ] - VTHN = 5V - ¡Ì(2 * 1.2?A)/(50?A/V2 * (1.5/8.55)) - 0.617V = 3.85V
Calculations: - Calculation of the gain for the current mirror transistors M1, M2, M7 3. To determine W1: Finally, we calculate the size of transistor M1. It's required that Iin = Iout. Consequently, the current conveyor ought to have I1 = I2,7. Assuming L1= L2,7:
Layout
PRE-LAYOUT DC INPUT TEST
Post-layout Line Regulation (Changing input voltage)
Post-layout Line Regulation (Changing input voltage)
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Low dropout regulator(ldo)

  • 1. ECE5590 AN Low Dropout Regulator(LDO) -Aadit Modi(ID#16037399) -Altaf Hirani (ID#12197304)
  • 2. LDO ? Linear Voltage DC regulators. ? Regulation maintained with small differences. ? Output current in range of 50-100mA. ? Pass transistor, error amplifier and voltage reference. ? Low quiescent current.
  • 3. ?Design a low dropout voltage regulator to provide an output voltage of 3.3V. Goals:
  • 4. For the calculations we assume the following constants: ? - Pass transistor current = 1mA ? - Vout = 3.3V ? - Dropout voltage ? - VDD=5V
  • 5. Block Diagram ? Pass transistor & error amplifier.
  • 6. CALCULATIONS: Efficiency calculation Iq (quiescent current) = 112 uA Io (output current) = 1.39 mA Vo (output voltage) = 3.37 V Vi (input voltage) = 5 V Eff. = Io*Vo/(Io + Iq)*Vi x 100 Using the above equation yields and efficiency of about 61.1%.
  • 7. - Summary of calculated transistor sizes vs the transistor simulation sizes TransistTor Calculated Size Actual Size Used Width(?m) Length(?m) Width(?m) Length(?m) M1 100 0.6 100.05 0.6 M2 100 0.6 100.05 0.6 M3 50 0.6 49.95 0.6 M4 50 0.6 49.95 0.6 M5 20 0.6 19.95 0.6 M6 250 0.6 250 0.6 TRANSISTOR SIZE TABLE
  • 10. Calculations: - Calculation of a range of Vbias1 1. To find Ibias1: From the desired a photodiode range, the minimum value of Ibias1: VGS3 =Vphmin Ibias1 = ? K1(W/L)3 (VGS3 -VTHN )2 = ? * 50 * 10-6 A/V2 * 3?m/0.6?m * (0.8V ¨C 0.617)2 = 4.186?A =4?A The maximum value of Ibias1: Ibias1 = ? K1(W/L)3 (VGS3 -VTHN )2 = ? * 50 * 10-6 A/V2 * 3?m/0.6?m * (3.0V ¨C 0.617)2 =0.7mA
  • 11. Calculations: - Calculation of sizes of the transistors M5, M4 1. To determine W5 From requirement to keep M5 in saturation region: VTH ¡ÜVGS5 = Vbias1(min) + VTHp ¨C Vph (max) = 2.8V +0.9V ¨C 3.0V = 0.7V W5 = (2InL5 )/(K1 (VGS5 -VTHN )2 ) = (2 * 1.2?A * 0.6?m)/(50?A/V2 * (0.7V ¨C 0.617V)2 ) = 4?m
  • 12. Calculations: - Calculation of sizes of the transistors M5, M4 2. To determine W4 VDS4 ¡ÝVGS4 ¨C VTHN VDS4 = Vph (min) = 0.8V Assumed VGS4 = 0.75V W4 = (2InL4 )/(K1 (VGS4 -VTHN )2 ) = (2 * 1.2?A * 0.6?m)/(50?A/V2 * (0.75V ¨C 0.617V)2 ) = 1.60?m
  • 13. Calculations: - Calculation of the gain for the current mirror transistors M1, M2, M7 1. To find VGS for M1, M2, M7 VGS1 = VDS1 = VGS2 = VGS1 = ¡Ì[(2Iout)/(K2 (W/L)2,7 ] + VTHp = ¡Ì(2 * 1.2?A)/(25?A/V2 * (20/2.4)) + 0.915V = 0.107V + 0.915V = 1V
  • 14. Calculations: - Calculation of the gain for the current mirror transistors M1, M2, M7 2. To find VDS for current mirror: Next we find VDS2 and VDS7 (which are the same in value) VDS2,7 = VDD ¨C VDS6 = VDD - ¡Ì[(2Iout)/(K1 (W/L)6 ] - VTHN = 5V - ¡Ì(2 * 1.2?A)/(50?A/V2 * (1.5/8.55)) - 0.617V = 3.85V
  • 15. Calculations: - Calculation of the gain for the current mirror transistors M1, M2, M7 3. To determine W1: Finally, we calculate the size of transistor M1. It's required that Iin = Iout. Consequently, the current conveyor ought to have I1 = I2,7. Assuming L1= L2,7:
  • 18. Post-layout Line Regulation (Changing input voltage)