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Polyphony
Python 匹反元戶月 FPGA
�躂
2017/9/9

失斥尼件母
? FPGA 勻化卅卞ˋ
? Polyphony ⻌嬡
? 妏勻化心方丹 Polyphony
每 Polyphony 𡛟蚚瞰(RISC-V)
每龰曰瞎心ㄠ(CNN)
每龰曰瞎心ㄡ(CV)
? 媆嶲互丐木壬民亙奈玄伉失伙
? 引午戶

赻撩畿賡
? @ryos36
? 甩永扑亙正弘
#polyphony
翍氪
匹允

FPGA 化卅卞ˋ
FPGA 毛妏勻化心方丹ㄐㄐ

FPGA 匹甩奈玉它尼失卞赻蚕僅毛ㄐ
http://www.ni.com 方曰
Wikipedia 方曰
FPGA=
Field-Programmable Gate Array

妏蚚瞰(OLED)
OLED 手仿奶皮仿伉互
丐日井元戶丐月
Jupyter 井日戊件玄伕奈伙

FPGA 午 WiFi 諉適瞰
皮伊永玉示奈玉匹
皿伕玄正奶皿及嶱逃

FPGA 及杻釾
腕砩卅仇午
? �K蹈�呾
? 伊奶氾件扑毛忐月仇午
? 申永玄�呾
? ⺥�俶
祥腕砩卅仇午
? 詢厒�I燴ˋ

FPGA vs Raspberry PI
? FPGA ? Raspberry PI
ARM SoCARM SoC FPGA
u-boot & Linuxu-boot & Linux
Linux Driver Linux Driver
Python Python
支曰凶中仇午支曰凶中仇午
�僇午井秏愐�薯午井⻌忒俶午井毛剠�仄化﹜末白玄腔卞介勻仁曰午掀廌
戊立亙瓦氾奴及湮五今ㄗロ�及⻌曰支允今ㄘ手分中少綃丹仃升﹜﹜﹜

HDL 匹睡井灍蚾仄化心方丹!?
? 妏丹晟惤
每 VHDL
每 Verilog HDL
LED 民市民市=L民市
甩奈玉它尼失及
Hello World 腔湔婓

FPGA匹甩奈玉它尼失毛赻蚕卞瞎戈
module fulladder
(
input x,
input y,
input cin,
output A,
output cout
);
assign {cout,A} = cin + y + x;
endmodule
甩奈玉它尼失�扴晟惤

VHDL 毛妏勻凶�觳
signal x: std_logic
＃
process (clk)
variable y : std_logic;
begin
if clk＊event and clk = 1 then
y := x + 1
x <= x + 1
end if;
end process;
Q: x 反中引 3 午仄引允﹝
酘煘卞丐月 y 午 x 反
中仁勾卞卅月匹仄斤丹ˋ

VHDL 毛妏勻凶�觳
signal x: std_logic
＃
process (clk)
variable y : std_logic;
begin
if clk＊event and clk = 1 then
y := x + 1
x <= x + 1
end if;
end process;
A:
y 反 4﹜
x 反 3及引引﹝
棒及弁伕永弁匹 4﹝
睡毛砩庤仄化中
月及井ˋ

FPGA 匹由奶皿仿奶件�I燴
�I燴 �I燴 �I燴 �I燴 �I燴
�I燴毛�煦趙允月仇午匹詢厒趙互褫夔
x + 1
x
x + 1
x
螹及笢匹左奈田仿永皿允月媆嶲毛
蕉尹卅互日偞�允月!!
睡毛砩庤仄化中
月及井ˋ

FPGA 及偞� = 螹及笢卞仇氏卅及互
佷中腹井少斛猁丐曰

踏匹手𨈘偩卞反疏倛毛獗月

仇仇引匹及引午戶
? FPGA 卅氏分井㜭仄公丹
? FPGA 切斤勻午褣仄公丹

Polyphony⻌嬡
Python 匹 FPGA

FPGA 勾井勻化心凶中仃升

Polyphony毛妏云丹!!
? PolyphonyㄩPython 匹甩奈玉它尼失偞�!

What is Polyphony?(1/3)
Python for Hardware Design
Python Polyphony
Verilog HDL
(synthesizable)

Python Polyphony
Verilog HDL
(synthesizable)
♂ Bring higher level of abstraction to your design
♂ Allow designers to focus on developing the algorithm
♂ Reduce costs for program maintenance
♂ Open Source (https://github.com/ktok07b6/polyphony)

Polyphony 反Python戊奈玉及
扔皮本永玄毛磁傖褫夔
Python
Polyphony
(is a subset of Python)
Function
Class
List(Fixed
size)
Tuple
For/While
If/Else
...
String
Dictionary
Set
Builtin funcs
...

引內反 L民市﹜﹜﹜
? 仇氏卅覜元匹匹五引允
from polyphony import testbench, module, is_worker_running
from polyphony.io import Bit
@module
class Blink:
def __init__(self):
self.led = Bit(0)
self.append_worker(self.main, led)
def main(self):
led = 1
while is_worker_running():
self.led.wr(led)
led = ~led
self._wait(10000000)
def _wait(self, interval):
for i in range(interval):
pass
blink = Blink()

Fibonacci Number(白奴示瓜永民杅蹈)
#from polyphony import testbench
def fib(n):
if n <= 0: return 0
if n == 1: return 1
r0 = 0
r1 = 1
for i in range(n-1):
prev_r1 = r1
r1 = r0 + r1
r0 = prev_r1
return r1
#@testbench
def test():
expect = [0,1,1,2,3,5,8,13,21,34,55,89,144,233,377,610]
for i in range(len(expect)):
result = fib(i)
assert expect[i] == result
print(i, "=>", result)
test()

仇仇引匹及引午戶
? Polyphony 匹 FPGA 互��g卞妏尹公丹
? Polyphony 匹睡互匹五月ˋ
? 升仇引匹匹五月ˋ

妏勻化心方丹 Polyphony
? 頄蜓卅仿奶皮仿伉
仇木井日頄蜓卞卅月(分欠丹)

Polyphony 仿奶皮仿伉
? bitonic_sort : 田奶玄瓦永弁末奈玄及扔件皿伙
? chenidct : 2棒啋IDCT(欄戊扔奶件劐𡥼)
? adpcm : ADPCM及巨件戊奈母?犯戊奈母
? UART: printf 犯田永弘腔卅仇午互堤懂月
? SPI + A/D: 本件扔奈午及窣觓

切斤勻午迕�
@polyphony.pure
def bitonic_indices(size, blocks, offset):
for i in range(0, size):
if (i % (offset << 1)) >= offset:
continue
direction = ASCENDING if (i // blocks) % 2 == 0 else DESCENDING
ii = i + offset
yield i, ii, direction
? bitonic_sort : 田奶玄瓦永弁末奈玄及扔件皿伙
杻�e卅犯戊伊奈正
Python 卞方曰※�腔卞§隙繚�毛赻�汜傖

Polyphony 𡛟蚚瞰
? RISC-V
? CNN
? CV(戊件疋亙奈正?申斥亦件)

RISC-V
RISC-V:湮忒き𦲀手蛁醴允月左奈皿件卅 CPU 及�跡﹝
允匹卞 FPGA 奻匹手�中化﹜Linux 手�釬允月耀�﹝

RISC-V on Polyphony
由奶皿仿奶件及扑立亙伊奈玄

CNN
Python 匹悝少犯奴奈皿仿奈瓦件弘及掛

CV(戊件疋亙奈正?申斥亦件)
CV 午網少卞反最罫中﹝
OpenCV 午及窣觓反※匹五引六氏§﹝
丐仄井日內﹝
巨永斥𨈘堤

民亙奈玄伉失伙
? Hello World
? Mul and Add
? 灍辻!!

Hello World 1
? 巨犯奴正奈匹 Hello World 毛迡仄引仄斤丹(迡磊)﹝
from polyphony import testbench
def hello():
print("Hello World.")
@testbench
def test():
hello()
test()

Hello World 2
? Python3 匹灍俴
每斛內 Python3 匹灍俴允月方丹卞仄引允
> python3 hello.py
Hello World.

Hello World 3
? Polyphony 匹戊件由奶伙
每 polyphony 匹戊件由奶伙仄引允﹝
> polyphony hello.py
> ls *.v
hello.v polyphony_out.v test.v
verilog 及白央奶伙(.v 及白央奶伙) 互汜傖今木引允﹝

Hello World 4
? iverilog 匹戊件由奶伙&灍俴
> iverilog -o hello polyphony_out.v test.v
[test-0.3.0] Persimmon:Tutorial_0> ls hello
hello*
> ./hello
0:
Hello World.
Hello World.
Hello World.
Hello World.
150:finish
Hello World
Hello World 互5隙灍俴今木月及互𠸎卞卅月源反

Mul and Add1
? 巨犯奴正奈匹 Hello World 毛迡仄引仄斤丹(迡磊)﹝
from polyphony import testbench
def mul_add(a, b, c, d):
return a * b + c * d
@testbench
def test():
assert 17 == mul_add(1, 2, 3, 4)
assert 62 == mul_add(4, 5, 6, 7)
test()

Mul and Add 2
? Python3 匹灍俴
每斛內 Python3 匹灍俴允月方丹卞仄引允
> python3 mul_add.py
Traceback (most recent call last):
File "mul_add.py", line 11, in <module>
test()
File "/lib/... .../polyphony/__init__.py", line 30, in _testbench_decorator
func()
File "mul_add.py", line 8, in test
assert 17 == mul_add(1, 2, 3, 4)
AssertionError
AssertionError 匹允﹝17 匹反卅仁 14 卞劐尹化婬僅民乓伊件斥

Mul and Add 3
? 扑立亙伊奈正匹灍俴
> ../bin/simu.py mul_add.py
0:mul_add_0_in_a= x, mul_add_0_in_b= x, mul_add_0_in_c= x,
mul_add_0_in_d= x, mul_add_0_out_0= x
10:mul_add_0_in_a= 0, mul_add_0_in_b= 0, mul_add_0_in_c= 0,
mul_add_0_in_d= 0, mul_add_0_out_0= 0
220:finish

灍辻匹反ˋ
? 磁傖仄化
? IO 饜�仄化
? 灍蚾仄化
? 末白玄手𤩸中化
每お�允月及卞末白玄午井斛猁井手

Python 匹白奴伙正�I燴
SPI SPI
I/F
SPI
I/F
白伊奈丞伐奈弁
#from polyphony import testbench
def filter(spi_in, spi_out):
....
....
SPI
Python 匹𤩸中凶白奴伙正奈互
FPGA 奻匹�仁!!
詢弇磁傖汁奈伙ㄩ

嶱逃平永玄
白伊奈丞伐奈弁
Murata
(LoRa�𡛟乒斥亙奈伙
SX1276 + Cortex-M0)
Kiss4
(Zynq = ARM + FPGA)
OR

Xilinx 及汁奈伙尺及�𡛟手仄引仄凶
ARM 皿伕本永扔 Polyphony 及
␌民市?乒斥亙奈伙

云引仃ㄩ犯奴奈皿仿奈瓦件弘
ARM
Cortex-M4
乒犯伙毛亢文勻午
㇌窺
3 FPGA

Polyphony 及踏摽
? HPC
每戶介六儔 �𡛟!!
? 旦氾伊左申斥亦件
每 �船賒砉
? Bayes
每丟奈伙及腢�e
? 杅��呾
每儕僅悵偩葆五ˋ

引午戶
? FPGA 勾井勻化心方丹!!
? Polyphony 毛妏尹壬
Python 及戊奈玉毛 HDL 卞!!
? Happy Python Life!!

仇木井日手 Polyphony 毛方欠仄仁!!
仍ラ�丐曰互午丹仍介中引仄凶

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Polyphony: Python 匹反元戶月 FPGA

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Polyphony: Python 匹反元戶月 FPGA