Sap 2 OF MICROPROCESSOR
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This document describes the architecture of the SAP-2 microprocessor. It has bidirectional registers that can either load or enable their outputs. The input and output pins are shorted together through a single set of wires. The architecture includes a 16-bit program counter, 2K ROM, 62K RAM, 8-bit instruction and data registers, and ALU with flags. It has temporary, B, and C registers and input/output ports for keyboard, display, and serial I/O. The document lists microprocessor instructions like LDA, STA, MVI, MOV, ADD, SUB, INR, DCR, JMP, CALL, CMA, AND, OR, XOR, ANI, OR
Sap 2 OF MICROPROCESSOR
- 1. SAP-2
- 2. Bidirectional Registers • Either enable or load only active . • During load input lines active output line float • During Enable output lines active input line float. • Input and output pins are shorted. • Single set of wires(path) between register and w-bus.
- 3. Architecture
- 4. Input port Port 1 and Port 2 Port 1 • Hexadecimal keyboard encoder • Sends ready signal to bit 0 of port 2 (indicates the data in port 1 is valid) Port 2 Serial In
- 5. Program Counter 16 bit address Thus can count from PC= 0000 0000 0000 0000 PC= 1111 1111 1111 1111(FFFFH) LOW CLR’
- 6. MAR and MEMORY 16- bit address to MAR(From ???). • MAR OUTPUT to RAM • Memory Capacity(?????) • 2K ROM(0000H-07FFH) => Monitor Program • 62K RAM(0800H-FFFFH)
- 7. Memory Data Register • 8-bit Register • Output setup RAM • Receives data from the bus before write operation • Data to the bus after read operation
- 8. Instruction Register • 8-bit op code • Can accommodate 256 instruction • Only 42 instruction
- 9. Controller Sequencer As usual • Generates the control words (microinstructions) • Has more hardware(larger number of instruction) • Control Word is bigger (CON)
- 11. ALU and Flags ALU :- Includes both arithmetic and logical operation 4 or more control bits for determining the operation to be performed Flag: Represent the status of the arithmetic and logical operation Filp flops are used; Zero Flag(Z) Sign Flag(S)
- 12. Temp,B,and C registers Temporary register (TEMP) Register B and C are used to move data during program run and accessible to programmers.
- 13. Outport Ports 2 output ports(3 and 4) Port 3 : Drives Hexadecimal display Port 4: sends ACKNOWLEDGE signals used to hexadecimal encoder.(Handshaking) Serial Out: Serial Transmission of data.
- 14. Microprocessor Instruction LDA and STA Eg: LDA 2000H STA 8000H
- 15. MVI MVI-Move Immediate MVI A,37H MVI A,byte MVI B,byte MVI c, byte
- 16. Register Instruction MOV MOV A,B MOV A,C MOV B,A MOV B,C MOV C,A MOV C,B
- 17. Register Instruction ADD and SUB Eg ADD B /SUB B ADD B ADD C SUB B SUB C
- 18. Register Instruction INR and DCR INR A/DCR A INR B/DCR B INR C/DCR C
- 19. Jump And Call Instruction JMP JMP 3000H JM (Jump if Minus) JZ(Jump if zero) JNZ(Jump if not zero)
- 20. Jump And Call Instruction CALL Subroutine ???? Call is used to call the subroutine Ret Return back from subroutine Program Counter contents ???? -----stored in the last two location of memory (FFFEH and FFFFH)
- 21. Logic Instruction CMA-Complement the accumulator ANA-And the accumulator with specified register eg ANA B ORA- OR the accumulator with specified register eg ORA B XRA- XOR the accumulator with specified register eg XRA B
- 22. ANI: And Immediate Eg ANI C7H (AND accumulator with immediate data C7H) ORI: OR immediate Eg ORI C7H XRI: XOR immediate Eg XRI C7H
- 23. Other Instruction OUT ( OUT byte eg: OUT 03H: accumulator to designated port) HLT IN(Input : Enter the data from designated input port to accumulator) eg: IN 02H NOP RAL(Rotate the accumulator left) A=1011 0100 After execution A=0110 1001 RAR (Rotate the accumulator right) A= 1011 0100 After execution A=0101 1010