Wyv7
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This document discusses a technique for reducing the height of the partial product array in radix-4 Modified Booth encoded two's complement multipliers without increasing the delay of the partial product generation stage. This reduction can allow for faster compression of the partial product array and more regular layouts. The method is general and can be applied to higher radix encodings and various multiplier sizes. Evaluation through theoretical analysis and logic synthesis showed the technique is efficient in terms of area and delay.
Wyv7
- 1. WYV7 www.wineyard.in Abstract: Twos complement multipliers are important for a wide range of applications. In this paper, we present a technique toreduce by one row the maximum height of the partial product array generated by a radix-4 Modified Booth Encoded multiplier, withoutany increase in the delay of the partial product generation stage. This reduction may allow for a faster compression of the partialproduct array and regular layouts. This technique is of particular interest in all multiplier designs, but especially in short bit-width twoscomplement multipliers for high-performance embedded cores. The proposed method is general and can be extended to higher radixencodings, as well as to any size square and m n rectangular multipliers. We evaluated the proposed approach by comparison withsome other possible solutions; the results based on a rough theoretical analysis and on logic synthesis showed its efficiency in terms ofboth area and delay. Language: Verilog HDL. Tools: Synthesis - XiLinx ISE 9.1. nd Hyderabad: Tarakarama Estates, 2 Left Lane Opp RS Brothers, Ameerpet, Hyderabad 500073 www.WineYard.in Ph: 040 6464 6363, 6625 6695, 888 5555 212 Reducing the computation time in (short bit width) twos compliment multipliers.